Isolation for non-volatile memory cell array

• US 8,072,023 B1
• Filed: 10/31/2008
• Issued: 12/06/2011
• Est. Priority Date: 11/12/2007
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Ingham, John C
• Application Number:
  US12/262,599
• Time in Patent Office: 1,131 Days
• Field of Search: 257/314, 257/321, 257/E29.304, 257/E21.206, 257/E21.545, 365/63, 438/266
• US Class Current: 257/321
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.

Claims

1. A memory device, comprising:

a plurality of storage regions arranged with storage region intervals,

a plurality of conductor lines, and

one or more isolations, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions,

wherein the storage regions include tunneling gates, and wherein the conductor lines include i) a plurality of first tunneling lines for electrically coupling the tunneling gates and ii) dummy tunneling lines in proximity to the isolations.

2. The memory device of claim 1, wherein the storage regions are charge storage regions in memory cells, and wherein each memory cell further includes a first cell region, a second cell region, and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region.

3. The memory device of claim 2, further including a first array region and a second array region separated by a first one of the isolations, each array region including one or more groups of the memory cells where each memory cell includes one of the storage regions.

4. The memory device of claim 2, wherein the conductor lines include first conductor lines extending in a first direction, and wherein the conductor lines further include second conductor lines extending in a second direction for electrically coupling the charge storage regions of a plurality of memory cells.

5. The memory device of claim 4, further including contacts electrically coupling the second conductor lines.

6. The memory device of claim 5, wherein each contact is juxtaposed an isolation and is located adjacent a dummy storage region.

7. The memory device of claim 5, wherein the contacts connect to metallization lines.

8. The memory device of claim 4, further including:

a first contact electrically coupling a first one of the second conductor lines in proximity to a first isolation, and

a second contact electrically coupling a second one of the second conductor lines in proximity to a second isolation.

9. The memory device of claim 1, wherein the isolation is an STI isolation or a LOCOS isolation.

10. The memory device of claim 1, wherein for one or more isolations, two or more of the dummy tunneling lines extend in a first direction and one or more connecting lines extend in a second direction and connect two of the dummy tunneling lines.

11. A memory device, comprising:

a plurality of memory cells, each memory cell including a first cell region, a second cell region, a cell channel between the first cell region and the second cell region, and a charge storage region,

a plurality of conductor lines,

one or more groups of the memory cells and including for each memory cell in a group,

a first one of the conductor lines aligned with the first cell region,

a second one of the conductor lines aligned with the second cell region,

the charge storage region juxtaposed a channel between the first one of the conductor lines and the second one of the conductor lines, and

one or more isolation regions, each isolation region juxtaposed one or more charge storage regions for one or more memory cells, each isolation region adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions,

wherein the memory cells include tunneling gates, and wherein the conductor lines include i) a plurality of first tunneling lines for electrically coupling the tunneling gates in array regions and ii) a plurality of second tunneling lines in the isolation regions.

12. The memory device of claim 11, wherein a second one of the conductor lines for memory cells in a first group is a first one of the conductor lines for memory cells in a second group.

13. The memory device of claim 11, wherein the one or more groups of the memory cells are arrayed in one or more of the array regions, wherein the array regions include a first array region and a second array region, and wherein one of the isolation regions separates the first array region and the second array region.

14. The memory device of claim 11, including for each memory cell a tunneling gate region in proximity to the charge storage region.

15. The memory device of claim 14, wherein the tunneling gate region includes a filter, a tunneling gate, and an insulator region.

16. The memory device of claim 11, wherein the first one of the conductor lines, the second one of the conductor lines, a third one of the conductor lines and a fourth one of the conductor lines are first conductor lines extending in a first direction, and wherein the memory device further includes second conductor lines extending in a second direction for electrically coupling the charge storage regions of the plurality of memory cells.

17. The memory device of claim 11, wherein the first one of the conductor lines and the second one of the conductor lines are first conductor lines extending in a first direction, and wherein the memory device further includes second conductor lines extending in a second direction through the array regions and through the isolation regions.

18. The memory device of claim 11, further including contacts electrically coupling second conductor lines in isolation regions.

19. The memory device of claim 11, wherein for one or more isolation regions, two or more of the second tunneling lines extend in a first direction and one or more connecting lines extend in a second direction and connect two or more of the second tunneling lines.

20. The memory device of claim 11, wherein each memory cell includes a tunneling gate region in proximity to the charge storage region.

21. The memory device of claim 11, wherein the first one of the conductor lines and the second one of the conductor lines are first conductor lines extending in a first direction, and wherein the memory device further includes second conductor lines extending in a second direction through the array regions and through the isolation regions.

22. The memory device of claim 11, further including:

a first contact electrically coupling a first one of the second conductor lines in a first isolation region, and

a second contact electrically coupling a second one of the second conductor lines in a second isolation region.

23. A method of arranging a memory device, the method comprising:

arranging a plurality of memory cells, each memory cell including a first cell region, a second cell region, a cell channel between the first cell region and the second cell region, and a charge storage region,

arranging a plurality of conductor lines,

arranging one or more groups of the memory cells and including for each memory cell in a group,

arranging a first one of the conductor lines connecting with the first cell region,

arranging a second one of the conductor lines connecting with the second cell region,

arranging the charge storage region juxtaposed the channel between the first one of the conductor lines and the second one of the conductor lines, and

arranging one or more isolation regions, each isolation region juxtaposed one or more charge storage regions for one or more memory cells, each isolation region adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions

providing tunneling gates in the memory cells, wherein the conductor lines include i) a plurality of first tunneling lines for electrically coupling the tunneling gates in array regions and ii) a plurality of second tunneling lines in the isolation regions.