3D channel architecture for semiconductor devices

• US 8,072,027 B2
• Filed: 06/08/2009
• Issued: 12/06/2011
• Est. Priority Date: 06/08/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Dan, Ho, Ihsiu, Sapp, Steven, Jo, Seokjin, Larsen, Mark, Kim, Suku, Kinzer, Dan, Challa, Ashok
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US12/480,065
• Publication Number:
  US 20100308402A1
• Time in Patent Office: 911 Days
• Field of Search: 257/331, 257/E29.257, 257/E29.26, 257/332
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate containing a source region in an upper portion of the substrate;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains;

a plurality of discrete lower trenches separated by a mesa between adjacent lower trenches, the lower trenches having sidewalls extending in both an x- and a y-direction; and

an upper trench overlying the lower trenches, the upper trench having sidewalls extending in the y direction that are longer than the sidewalls extending in the x direction;

an oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a first conductive or semi-conductive layer located on the oxide layer in the lower trenches; and

a second conductive or semi-conductive layer located on the first conductive or semi-conductive layer and the mesa.

2. The device of claim 1, wherein the device contains channels extending in the x and y directions and in a z directions to form a three dimensional channel structure.

3. The device of claim 1, wherein an upper portion of the lower trenches opens into a lower portion of the upper trench.

4. The device of claim 1, wherein the oxide layer is also located on an upper portion of the mesa.

5. The device of claim 1, wherein the width of the lower trenches in the x direction is more than the length of the mesa separating adjacent lower trenches.

6. The device of claim 1, wherein a width of the lower trenches ranges from about 0.01 to about 10 μ

m and a length ranges from about 0.01 to about 10 μ

m.

7. The device of claim 1, wherein the first and second conductive or semi-conductive layers are formed from the same material and form a continuous layer or formed from a different material and form two separate layers.

8. The device of claim 7, wherein the first conductive or semi-conductive layer is deposited to cover the mesa and the second conductive or semi-conductive layer is deposited on that first layer.

9. A trench MOSFET device containing a three dimensional channel architecture, comprising:

a silicon substrate with an epitaxial layer in an upper portion thereof, the epitaxial layer containing a source region in an upper portion thereof;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains;

a plurality of discrete lower trenches separated by a mesa between adjacent lower trenches, the lower trenches having sidewalls extending both in an x- and a y-direction; and

an upper trench overlying the lower trenches, the upper trench having sidewalls extending in the y direction that are longer than the sidewalls extending in the x direction;

a gate oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a polysilicon gate located on the gate oxide layer in the lower trenches;

a conductive layer located on the polysilicon gate and the mesa and in the upper trench; and

an insulating layer located on the conductive layer in the upper trench between the source region.

10. The device of claim 9, wherein the device contains channels extending in the x and y directions and in a z directions to form a three dimensional channel structure.

11. The device of claim 10, wherein the current flows through the dual trench structure in three dimensions.

12. The device of claim 9, wherein the oxide layer is also located on an upper portion of the mesa.

13. The device of claim 9, wherein a width of the lower trenches in the x direction is more than a length of the mesa separating adjacent lower trenches.

14. The device of claim 9, wherein a width of the lower trenches ranges from about 0.01 to about 10 μ

m and a length ranges from about 0.01 to about 10 μ

m.

15. The device of claim 9, wherein the first and second conductive or semi-conductive layers are formed from the same material and form a continuous layer or are formed from a different material and form two separate layers.

16. The device of claim 9, further comprising a shield oxide layer and a conductive shield around the epitaxial layer.

17. The device of claim 9, wherein the oxide layer is also located on an upper portion of the mesa.

18. The device of claim 9, wherein a width of the lower trenches in the x direction is more than a length of the mesa separating adjacent lower trenches.

19. The device of claim 9, wherein a width of the lower trenches ranges from about 0.01 to about 10 μ

m and a length ranges from about 0.01 to about 10 μ

m.

20. The device of claim 9, wherein the first and second conductive or semi-conductive layers are formed from the same material and form a continuous layer or are formed from a different material and form two separate layers.

21. The device of claim 9, further comprising a shield oxide layer and a conductive shield around the epitaxial layer.

22. A trench MOSFET device containing a three dimensional channel architecture, comprising:

a silicon substrate with an epitaxial layer in an upper portion thereof, the epitaxial region layer containing a source region in an upper portion thereof;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains;

a plurality of discrete lower trenches separated by a mesa between adjacent lower trenches, the lower trenches having sidewalls extending in both an x- and a y-direction; and

an upper trench overlying the lower trenches, the upper trench having sidewalls extending in the y direction that are longer than the sidewalls extending in the x direction;

thereby forming channels extending in the x and y directions and in a z direction and making a three dimensional channel structure so that current flows through the dual trench structure in three dimensions;

a gate oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a polysilicon gate located on the gate oxide layer in the lower trenches;

a conductive layer located on the polysilicon gate and the mesa and in the upper trench; and

an insulating layer located on the conductive layer in the upper trench between the source region.

23. A semiconductor device, comprising:

a semiconductor substrate containing a source region in an upper portion of the substrate;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains with a plurality of lower trenches extending in both x- and y-directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate the source region;

wherein the width of the lower trenches in the x direction is more than the length of the mesa separating adjacent lower trenches,

an oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a first portion of a conductive or semi-conductive layer located on the oxide layer in the lower trenches; and

a second portion of a conductive or semi-conductive layer located on the first conductive layer and the mesa.

24. The device of claim 23, wherein the current flows through the dual trench structure in three dimensions.