Semiconductor device with increased I/O leadframe including passive device

• US 8,072,050 B1
• Filed: 11/18/2008
• Issued: 12/06/2011
• Est. Priority Date: 11/18/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Karim, Nozad O., Olson, Timothy L.
• Primary Examiner(s): Hoang, Quoc D
• Assistant Examiner(s): Tran, Tony
• Application Number:
  US12/273,500
• Time in Patent Office: 1,113 Days
• Field of Search: 237666-677
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49589 Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die pad and a plurality of leads. Some of these leads include exposed bottom surface portions or lands which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. A passive device may be electrically connected to and extend between the die pad and one of the leads, and/or may be electrically connected to and extend between and adjacent pair of the leads.

Claims

1. A semiconductor package comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being disposed in spaced relation to the die pad;

a plurality of second leads, at least some of which include a downset formed therein, the second leads being disposed in spaced relation to the die pad;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second leads;

at least one passive component electrically connected to and extending between adjacent portions of the leadframe; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads, the semiconductor die and the passive component such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.

2. The semiconductor package of claim 1 wherein the at least one passive component comprises

a first passive component electrically connected to and extending between

an adjacent pair of the first leads.

3. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the first and second leads by conductive wires which are covered by the package body.

4. The semiconductor package of claim 3 wherein:

each of the first leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die pad and defining a land which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the second leads includes a wire bond zone and an outer end portion, the downset of each of the second leads extending between the wire bond zone and the outer end portion thereof;

and

the conductive wires extend from the semiconductor die to respective ones of the wire bond zones of the first leads and second leads.

5. The semiconductor package of claim 4 wherein:

the die pad and the inner end portions of the first leads extend along a first plane;

the wire bond zones of the first and second leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the outer end portions of the first and second leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

6. A semiconductor package comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads disposed in spaced relation to the die pad;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads being disposed in spaced relation to the die pad;

a plurality of third leads, at least some of which include a downset formed therein, the third leads being disposed in spaced relation to the die pad;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second and third leads;

at least one passive component electrically connected to and extending between adjacent portions of the leadframe; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads, the semiconductor die and the passive component such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die pad and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the third leads protrude from respective ones of the side surfaces of the package body.

7. The semiconductor package of claim 6 wherein at least some of the first leads are integrally connected to the die pad and define signal pins.

8. The semiconductor package of claim 6 wherein the at least one passive component comprises one or more of:

a first passive component electrically connected to and extending between one of the first leads and the die pad;

a second passive component electrically connected to and extending between an adjacent pair of the first leads;

a third passive component electrically connected to and extending between an adjacent pair of the second leads; and

a fourth passive component electrically connected to and extending between an adjacent pair of the first and second leads.

9. The semiconductor package of claim 8 wherein the fourth passive component is electrically connected to each of the first and second leads of the adjacent pair by a stand-off feature.

10. The semiconductor package of claim 6 wherein the semiconductor die is electrically connected to the first, second and third leads by conductive wires which are covered by the package body.

11. The semiconductor package of claim 10 wherein:

each of the first leads defines a land which is exposed in the bottom surface of the package body;

each of the second leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die pad and defining a land which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the third leads includes a wire bond zone and an outer end portion, the downset of each of the third leads extending between the wire bond zone and the outer end portion thereof; and

the conductive wires extend from the semiconductor die to respective ones of the first leads and the wire bond zones of the second leads and third leads.

12. The semiconductor package of claim 11 wherein:

the die pad, the first leads and the inner end portions of the second leads extend along a first plane;

the wire bond zones of the second and third leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the outer end portions of the second and third leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

13. A semiconductor package comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads which are disposed in spaced relation to the die pad;

a plurality of second leads which are disposed in spaced relation to the die pad;

a plurality of third leads which each include a downset formed therein, the third leads being disposed in spaced relation to the die pad;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second, and third leads;

at least one passive component electrically connected to and extending between adjacent portions of the leadframe; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second, and third leads, the semiconductor die, and the passive component such that the downsets of the third leads are covered by the package body, at least portions of the die pad and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the third leads protrude from respective ones of the side surfaces of the package body.

14. The semiconductor package of claim 13 wherein the at least one passive component comprises one or more of:

a first passive component electrically connected to and extending between one of the first leads and the die pad;

a second passive component electrically connected to and extending between an adjacent pair of the first and second leads;

a third passive component electrically connected to and extending between an adjacent pair of the first leads; and

a fourth passive component electrically connected to and extending between an adjacent pair of the second leads.

15. The semiconductor package of claim 14 wherein the second passive component is electrically connected to each of the first and second leads of the adjacent pair by a stand-off feature.

16. The semiconductor package of claim 13 wherein:

each of the first leads defines a land which is exposed in the bottom surface of the package body;

each of the second leads defines a land which is exposed in the bottom surface of the package body;

the die pad, and the lands of the first and second leads extend along a first plane; and

portions of the third leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.

17. A semiconductor package comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads which are disposed in spaced relation to the die pad;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads being disposed in spaced relation to the die pad;

a plurality of third leads which are disposed in spaced relation to the die pad;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second, and third leads;

at least one passive component electrically connected to and extending between adjacent portions of the leadframe; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second, and third leads, the semiconductor die, and the passive component such that the downsets of the second leads are covered by the package body, at least portions of the die pad and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the third leads protrude from respective ones of the side surfaces of the package body.

18. The semiconductor package of claim 17 wherein the at least one passive component comprises one or more of:

a first passive component electrically connected to and extending between one of the first leads and the die pad;

a second passive component electrically connected to and extending between an adjacent pair of the first and second leads;

a third passive component electrically connected to and extending between an adjacent pair of the first leads; and

a fourth passive component electrically connected to and extending between an adjacent pair of the second leads.

19. The semiconductor package of claim 18 wherein the second passive component is electrically connected to each of the first and second leads of the adjacent pair by a stand-off feature.

20. The semiconductor package of claim 17 wherein:

each of the first leads defines a land which is exposed in the bottom surface of the package body;

each of the second leads defines a land which is exposed in the bottom surface of the package body;

the die pad, and the lands of the first and second leads extend along a first plane; and

portions of the third leads extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.