Low fabrication cost, fine pitch and high reliability solder bump
First Claim
1. A chip comprising:
- a silicon substrate;
a dielectric layer over said silicon substrate;
an aluminum pad over said dielectric layer;
a topmost insulating layer of said chip over said dielectric layer, wherein an opening in said topmost insulating layer of said chip is over said aluminum pad, wherein said topmost insulating layer of said chip is a polymer layer; and
a metal bump on said aluminum pad and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a metal layer on said aluminum pad, in said opening and on said first top surface, a copper pillar on said metal layer, over said aluminum pad and over said first top surface, and a solder over said copper pillar, over said opening and over said first top surface, wherein said solder is connected to said copper pillar, wherein said copper pillar has a thickness between 10 and 100 micrometers, wherein said copper pillar has a second top surface higher than said first top surface and has a sidewall with a portion not covered by said solder.
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Accused Products
Abstract
A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
263 Citations
23 Claims
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1. A chip comprising:
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a silicon substrate; a dielectric layer over said silicon substrate; an aluminum pad over said dielectric layer; a topmost insulating layer of said chip over said dielectric layer, wherein an opening in said topmost insulating layer of said chip is over said aluminum pad, wherein said topmost insulating layer of said chip is a polymer layer; and a metal bump on said aluminum pad and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a metal layer on said aluminum pad, in said opening and on said first top surface, a copper pillar on said metal layer, over said aluminum pad and over said first top surface, and a solder over said copper pillar, over said opening and over said first top surface, wherein said solder is connected to said copper pillar, wherein said copper pillar has a thickness between 10 and 100 micrometers, wherein said copper pillar has a second top surface higher than said first top surface and has a sidewall with a portion not covered by said solder. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A chip comprising:
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a silicon substrate; a dielectric layer over said silicon substrate; an aluminum pad over said dielectric layer; a topmost insulating layer of said chip over said dielectric layer, wherein an opening in said topmost insulating layer of said chip is over said aluminum pad, wherein said topmost insulating layer of said chip is a polymer layer; and a metal bump on said aluminum pad and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a metal layer on said aluminum pad, in said opening and on said first top surface, and a copper pillar on said metal layer, over said aluminum pad and over said first top surface, wherein said copper pillar has a thickness between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar, wherein said copper pillar has a second top surface higher than said first top surface. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification