Pre-encapsulated cavity interposer

• US 8,072,082 B2
• Filed: 05/28/2008
• Issued: 12/06/2011
• Est. Priority Date: 04/24/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yean, Tay Wuu, Ai-Chie, Wang
• Primary Examiner(s): Chu, Chris
• Application Number:
  US12/128,575
• Publication Number:
  US 20090267171A1
• Time in Patent Office: 1,287 Days
• Field of Search: 438/64, 438/117, 438/125, 438/108, 438/109, 257/E23.019, 257/E23.066, 257/E23.128, 257/E23.031, 257/E31.11, 257/666, 257/690, 257/685, 257/686, 257/698, 257/432, 257/434, 257/723, 257/724, 257/778, 257/777, 257/E25.018, 257/E25.013, 257/E21.614, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1017 the lowermost container comprising a device support
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.

Claims

1. A semiconductor assembly including a pre-encapsulated frame, the assembly comprising:

a structure comprising an encapsulation material and having a cavity therein, the cavity having a portion of the structure extending thereover and another portion extending therearound;

at least two semiconductor devices located in the cavity of the structure; and

a plurality of traces located in the encapsulation material of the structure, each trace having an upper first portion extending in the portion of the structure extending over the cavity, a lower first portion extending in a direction parallel to the direction in which the upper first portion extends in the portion of the structure extending over the cavity, and a second portion extending in the another portion of the structure connected to the first portion, one end of the second portion being exposed for connection thereto,

wherein the upper first portion of at least one trace of the plurality of traces has a length greater than a length of the lower first portion of the at least one trace of the plurality of traces.

2. The assembly of claim 1, wherein the one end of the second portion of a trace of the plurality of traces includes at least one of one or more recesses therein and a roughened surface.

3. The assembly of claim 1, wherein the plurality of traces comprises:

a first plurality of traces having a first portion extending from one side of the structure across a portion of the cavity; and

a second plurality of traces having a first portion extending from another side of the structure across a portion of the cavity.

4. The assembly of claim 3, wherein the plurality of traces further comprise:

a third plurality of traces having a first portion extending from a third side of the structure across a portion of the cavity.

5. The assembly of claim 4, wherein the plurality of traces further comprise:

a fourth plurality of traces having a first portion extending from a fourth side of the structure across a portion of the cavity.

6. The assembly of claim 1, wherein the second portion of a trace includes two portions exposed from the structure.

7. The assembly of claim 1, wherein another end of a trace is exposed for connection thereto.

8. The assembly of claim 1, wherein the pre-encapsulated frame comprises one of a strip of pre-encapsulated frames.

9. The assembly of claim 1, wherein the pre-encapsulated frame comprises one of a panel of pre-encapsulated frames.

10. The assembly of claim 1, wherein at least one semiconductor device of the at least two semiconductor devices comprises a flip-chip type semiconductor device.

11. The assembly of claim 1, wherein at least one semiconductor device of the at least two semiconductor devices comprises a semiconductor device having at least one bond pad thereof connected to at least one trace using a bond wire.

12. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having bond pads in a one-sided layout and at least another semiconductor device.

13. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof in a 1.5 sided layout and at least another semiconductor device.

14. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof in a one sided layout along the long side of the semiconductor device and at least another semiconductor device.

15. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof in a two sided layout and at least another semiconductor device.

16. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof located essentially in the center of the semiconductor device and at least another semiconductor device.

17. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof located essentially in a single row in the center of the semiconductor device and at least another semiconductor device.

18. The assembly of claim 1, wherein the plurality of traces comprises a plurality of traces configured for connection to at least one semiconductor device having the bond pads thereof located essentially in multiple rows essentially in the center of the semiconductor device and at least another semiconductor device.

19. The assembly of claim 1, further comprising:

encapsulation material located in the cavity of the structure.

20. The assembly of claim 1, wherein the one end of the second portion of a trace of the plurality of traces includes one of a groove therein and a roughened surface thereon.

21. The assembly of claim 1, wherein the second portion of a trace of the plurality of traces comprises a plurality of portions, each portion having one end of the second portion exposed for connection thereto.

22. A semiconductor assembly including a pre-encapsulated frame, the assembly comprising:

a first structure comprising an encapsulation material and having a cavity therein, the cavity having a portion of the first structure extending thereover and another portion extending therearound;

a plurality of traces located in the first structure, each trace having a first portion having only a first length extending in the portion of the first structure extending over the cavity and a second portion extending in the another portion of the structure connected to the first portion, one end of the second portion being exposed for connection thereto,

wherein the first portion of at least one trace of the plurality of traces located in the first structure has a first length;

a first semiconductor device located in the cavity of the first structure;

a second structure comprising an encapsulation material and having a cavity therein, the cavity having a portion of the second structure extending thereover and another portion extending therearound;

a plurality of traces located in the second structure, each trace having a first portion having only a second, different length extending in a direction parallel to the direction in which the first portion of the plurality of traces of the first structure extends in the portion of the second structure extending over the cavity and a second portion extending in the another portion of the second structure connected to the first portion, one end of the second portion being exposed for connection thereto by the one end of the second portion of a trace of the plurality of traces of the first structure; and

a second semiconductor device located in the cavity of the second structure.

23. The assembly of claim 22, wherein the first semiconductor device comprises a NAND semiconductor memory device.

24. The assembly of claim 23, wherein the second semiconductor device comprises a DRAM semiconductor memory device.

25. The assembly of claim 22, wherein the first semiconductor device comprises a controller semiconductor device.

26. The assembly of claim 22, wherein the first semiconductor device comprises one of a controller semiconductor device and a NAND semiconductor memory device and the second semiconductor device comprises one of a NAND semiconductor memory device and a DRAM semiconductor memory device.

27. The assembly of claim 22, further comprising:

a substrate having circuits thereon connected to one of the first structure and the second structure.

28. A semiconductor assembly comprising a pre-encapsulated frame, the assembly comprising:

a structure comprising an encapsulation material and having a cavity therein, the cavity having a portion of the structure extending thereover and another portion extending therearound; and

a plurality of traces located in the structure, each trace having a first portion extending in the portion of the structure extending over the cavity and a second portion extending in the another portion of the structure connected to the first portion, one end of the second portion being exposed for connection thereto, the first portion of at least one trace of the plurality of traces connected to a first semiconductor device and the first portion of at least another trace of the plurality of traces connected to a second semiconductor device,

wherein the first portion of the at least one trace of the plurality of traces has a length greater than a length of the first portion of the at least another trace of the plurality of traces.

29. The assembly of claim 28, wherein the first semiconductor device comprises a semiconductor device adhesively attached to a portion of the structure and the second semiconductor device comprises a semiconductor device adhesively attached to a portion of the first semiconductor device.

30. A semiconductor assembly comprising a pre-encapsulated frame, the assembly comprising:

a structure comprising an encapsulation material and having a cavity therein, the cavity having a portion of the structure extending thereover and another portion extending therearound; and

a plurality of traces located in the structure, a first plurality of traces having a first length and a second plurality of traces having a second length, the first length being greater than the second length, each trace having a first portion extending in the portion of the structure extending over the cavity and a second portion extending in a direction parallel to the direction in which the upper first portion extends in the another portion of the structure connected to the first portion, one end of the second portion being exposed for connection thereto, the first portion of the first plurality of traces connected to a first semiconductor device and the first portion of the second plurality of traces connected to a second semiconductor device.

31. The assembly of claim 30, further comprising:

an encapsulant material located in the cavity.

32. The assembly of claim 30, wherein the first semiconductor device comprises a semiconductor device located above the second semiconductor device in the cavity.