System and method for providing a dynamically configured low drop out regulator with zero quiescent current and fast transient response

• US 8,072,196 B1
• Filed: 01/15/2008
• Issued: 12/06/2011
• Est. Priority Date: 01/15/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Li, Yushan
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Finch, III, Fred E
• Application Number:
  US12/008,852
• Time in Patent Office: 1,421 Days
• Field of Search: 323/268, 323/271, 323/277, 323/275, 323/266, 323/273, 323/282, 323/284
• US Class Current: 323/266
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A system and a method are disclosed for providing a dynamically configured low drop out regulator that has zero quiescent current and a fast transient response. A power supply control circuit is provided that comprises a switcher circuit and a low drop out regulator and a control signal circuit. When the output voltage of the low drop out regulator is in a steady state condition the control signal circuit generates control signals that turn off the operation of the low drop out regulator to provide zero quiescent current. When the output voltage is not in a steady state condition the control signal circuit generates control signals that turn on the operation of the low drop out regulator to provide a fast transient response.

Claims

1. A power supply control circuit comprising:

a low drop out circuit comprising an operational amplifier, the operational amplifier having an output configured to be coupled to a low drop out transistor for generating a power supply output voltage at a first source/drain terminal of the low drop out transistor;

a switcher circuit having an output configured to be coupled to a second source/drain terminal of the low drop out transistor and to provide a switcher operating voltage to the low drop out transistor; and

control signal circuitry configured to regulate an operation of the low drop out circuit, the control signal circuitry further configured to turn off the low drop out circuit when the power supply output voltage is in a steady state condition;

wherein the control signal circuitry is configured to generate (i) a low drop out enable signal controlling whether the operational amplifier is enabled or disabled and (ii) a bypass signal controlling whether a bypass transistor couples a gate of the low drop out transistor to ground.

2. The power supply control circuit as set forth in claim 1, wherein the control signal circuitry is configured to determine whether the power supply output voltage is in the steady state condition.

3. The power supply control circuit as set forth in claim 2, wherein the control signal circuitry is configured to turn on the low drop out circuit when the power supply output voltage is not in the steady state condition.

4. The power supply control circuit as set forth in claim 2, wherein the control signal circuitry is configured to generate the low drop out enable signal having a high logical level and the bypass signal having a low logical level when the output voltage of the low drop out circuit is not in the steady state condition.

5. The power supply control circuit as set forth in claim 4, wherein the control signal circuitry is configured to use the low drop out enable signal and the bypass signal to turn on the low drop out circuit.

6. The power supply control circuit as set forth in claim 5, wherein the control signal circuitry is configured to use the low drop out enable signal to close a switch in the switcher circuit to couple a feedback voltage from the switcher circuit to an error amplifier of the switcher circuit.

7. The power supply control circuit as set forth in claim 2, wherein the control signal circuitry is configured to generate the low drop out enable signal having a low logical level and the bypass signal having a high logical level when the output voltage of the low drop out circuit is in the steady state condition.

8. The power supply control circuit as set forth in claim 7, wherein the control signal circuitry is configured to use the low drop out enable signal and the bypass signal to turn off the low drop out circuit.

9. The power supply control circuit as set forth in claim 8, wherein the control signal circuitry is configured to use the low drop out enable signal to close a switch in the switcher circuit to couple a feedback voltage from the low drop out circuit to an error amplifier of the switcher circuit.

10. A power supply control circuit comprising:

a low drop out circuit comprising an operational amplifier, the operational amplifier having an output configured to be coupled to a low drop out transistor;

a switcher circuit configured to provide a switcher operating voltage to the low drop out transistor; and

control signal circuitry configured to regulate an operation of the low drop out circuit, the control signal circuitry further configured to determine whether an output voltage of the low drop out circuit is in a steady state condition and to turn off the low drop out circuit when the output voltage of the low drop out circuit is in the steady state condition;

wherein the control signal circuitry comprises an inverter configured to generate a bypass signal and a logical AND gate configured to generate a low drop out enable signal.

11. A power supply control circuit comprising:

a low drop out circuit comprising (i) an operational amplifier having an output configured to be coupled to a low drop out transistor and (ii) a bypass transistor configured to couple a gate of the low drop out transistor to ground;

a switcher circuit configured to provide a switcher operating voltage to the low drop out transistor; and

control signal circuitry configured to generate at least one control signal that turns off the low drop out circuit and causes the bypass transistor to couple the gate of the low drop out transistor to ground when an output voltage of the low drop out circuit is in a steady state condition;

wherein the control signal circuitry is configured to disable the operational amplifier and activate the bypass transistor when the output voltage of the low drop out circuit is in the steady state condition; and

wherein the control signal circuitry is configured to enable the operational amplifier and deactivate the bypass transistor when the output voltage of the low drop out circuit is not in the steady state condition.

12. The power supply control circuit as set forth in claim 11, wherein the low drop out circuit is configured to generate zero quiescent current when the low drop out circuit is turned off.

13. The power supply control circuit as set forth in claim 11, wherein the control signal circuitry is further configured to generate at least one control signal that turns on the low drop out circuit when the output voltage of the low drop out circuit is not in the steady state condition.

14. The power supply control circuit as set forth in claim 13, wherein the low drop out circuit is configured to provide a fast transient response when the low drop out circuit is turned on.

15. A power supply control circuit comprising:

a low drop out circuit comprising an operational amplifier, the operational amplifier having an output configured to be coupled to a low drop out transistor;

a switcher circuit configured to provide a switcher operating voltage to the low drop out transistor; and

control signal circuitry configured to generate at least one control signal that turns off the low drop out circuit when an output voltage of the low drop out circuit is in a steady state condition;

wherein the control signal circuitry comprises an inverter configured to generate a bypass signal and a logical AND gate configured to generate a low drop out enable signal.

16. A power supply control circuit comprising:

a low drop out circuit comprising an operational amplifier, the operational amplifier having an output configured to be coupled to a low drop out transistor;

a switcher circuit configured to provide a switcher operating voltage to the low drop out transistor; and

control signal circuitry configured to generate a low drop out enable signal and a bypass signal that turn off the low drop out circuit when an output voltage of the low drop out circuit is in the steady state condition.

17. The power supply control circuit as set forth in claim 16, wherein the control signal circuitry is also configured to generate the low drop out enable signal and the bypass signal that turn on the low drop out circuit when the output voltage of the low drop out circuit is not in the steady state condition.

18. A method for operating a power supply control circuit, the method comprising the steps of:

providing, at a switcher circuit coupled to a low drop out circuit, a switcher operating voltage to a low drop out transistor, the low drop out circuit comprising an operational amplifier having an output coupled to the low drop out transistor;

generating, at control signal circuitry, at least one control signal for the low drop out circuit and the switcher circuit; and

using the at least one control signal to turn off the low drop out circuit when an output voltage of the low drop out circuit is in a steady state condition;

wherein generating the at least one control signal comprises;

generating a bypass signal; and

generating a low drop out enable signal.

19. The method as set forth in claim 18, wherein:

generating the bypass signal comprises using an inverter; and

generating the low drop out enable signal comprises using a logical AND gate.

20. The method as set forth in claim 18, further comprising the step of:

using the at least one control signal to turn on the low drop out circuit when the output voltage of the low drop out circuit is not in the steady state condition.

21. The method of claim 18, wherein:

the low drop out enable signal controls whether the operational amplifier is enabled or disabled; and

the bypass signal controls whether a bypass transistor couples a gate of the low drop out transistor to ground.