Micro-granular delay testing of configurable ICs

• US 8,072,234 B2
• Filed: 05/23/2010
• Issued: 12/06/2011
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Fox, Brian
• Primary Examiner(s): Tran, Anh
• Application Number:
  US12/785,484
• Publication Number:
  US 20110068820A1
• Time in Patent Office: 562 Days
• Field of Search: None
• US Class Current: 326/16
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Claims

1. A method for testing a set of circuitry in an integrated circuit (IC) comprising a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a plurality of configurable routing circuits for configurably passing signals among the circuits of the IC, a plurality of controllable storage elements for controllably storing signals as the signals transit between the configurable circuits, and a debug network that accesses the controllable storage elements, the method comprising:

configuring the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria, each test path comprising a set of configurable logic circuits, a set of configurable routing circuits, and at least one controllable storage element;

operating the IC in the user mode; and

reading values stored in the storage elements along the set of test paths through the debug network to determine whether the set of circuitry is operating within specified performance limits.

2. The method of claim 1 further comprising supplying a set of test vectors to the IC.

3. The method of claim 1, wherein at least one controllable storage element is a configurable storage element for controllably storing a signal that the storage element receives based on configuration data supplied to the storage element.

4. The method of claim 1, wherein at least one controllable storage element is a clocked storage element for controllably storing a signal that the storage element receives based on a clock signal supplied to the storage element.

5. The method of claim 1, wherein at least one test path comprises a routing multiplexer for controllable routing signals that the multiplexer receives.

6. The method of claim 1, wherein the specified performance limits comprise a set of timing constraints.

7. The method of claim 6, wherein the specified performance limits further comprise a set of expected logic values.

8. A method for testing an integrated circuit (IC) comprising a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a configurable routing fabric for passing signals among the circuits of the IC, a plurality of configurable storage elements placed throughout the configurable routing fabric for controllably storing signals passed along the configurable routing fabric, and a debug network that accesses the configurable storage elements, the method comprising:

configuring each circuit in a first set of configurable circuits to operate as a launch element;

configuring each circuit in a second set of configurable circuits to operate as a capture element; and

configuring a set of test paths, each test path comprising a set of circuitry included in the IC, wherein each test path is stimulated by a particular launch element and terminated at a particular capture element.

9. The method of claim 8 further comprising supplying a set of test vectors to the IC.

10. The method of claim 8, wherein at least one configurable circuit in the first set of configurable circuits comprises a look-up table.

11. The method of claim 8, wherein at least one configurable circuit in the first set of configurable circuits comprises a multiplexer.

12. The method of claim 8, wherein at least one configurable circuit in the first set of configurable circuits comprises a configurable storage element.

13. The method of claim 8 further comprising:

operating the IC in user mode, wherein operating the IC in user mode comprises supplying at least one clock signal to the IC after configuring the configurable circuits of the IC; and

reading values stored in the second set of configurable circuits through the debug network to determine whether each set of circuitry included in each test path is operating within specified performance limits.

14. The method of claim 13, wherein a first clock signal is supplied to the first set of configurable circuits, wherein a second clock signal is supplied to the second set of configurable circuits, wherein the first clock signal and the second clock signal have a particular phase offset.

15. The method of claim 14 further comprising adjusting the particular phase offset to determine a minimum phase offset required to meet the specified performance limits.

16. An integrated circuit (IC) comprising:

a first set of configurable circuits configured to operate as test stimulus elements;

a second set of configurable circuits configured to operate as test capture elements;

a third set of configurable circuits configured to operate as a set of test paths, each test path comprising a set of circuitry included in the IC, wherein each test path receives a signal from a particular test stimulus element and captures responses to the test stimulus element at a set of test capture elements along the test path, the set of test capture elements for each particular test path partitioning the particular test path into a plurality of segments; and

a debug network to retrieve and store signals stored in test capture elements in order to identify a segment of a test path where a malfunction has occurred.

17. The IC of claim 16, wherein the third set of configurable circuits comprises a routing multiplexer for configurably routing signals that the multiplexer receives.

18. The IC of claim 16, wherein at least one test stimulus element in the first set of configurable circuits comprises a look-up table.

19. The IC of claim 16, wherein at least one test stimulus element comprises a multiplexer.