Programmable voltage regulator

• US 8,072,247 B1
• Filed: 10/04/2007
• Issued: 12/06/2011
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Hernandez, William
• Application Number:
  US11/973,038
• Time in Patent Office: 1,524 Days
• Field of Search: 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Furthermore, the circuit can include a non-volatile memory that is coupled to the variable voltage generator. The non-volatile memory can be coupled to receive programming for controlling an output voltage of the variable voltage generator.

Claims

1. A circuit comprising:

a variable voltage generator coupled to receive an input voltage, wherein the variable voltage generator comprises a follower circuit, and wherein the follower circuit comprises an amplifier coupled with a switching element;

a non-volatile memory coupled to said variable voltage generator, said nonvolatile memory coupled to receive programming for controlling an output voltage of said variable voltage generator; and

a processing element coupled with the nonvolatile memory and the variable voltage generator.

2. The circuit of claim 1, wherein the follower circuit is coupled to receive said input voltage.

3. The circuit of claim 1, wherein said variable voltage generator is coupled to receive a reference voltage.

4. The circuit of claim 1, where said programming sets an output voltage for said circuit.

5. The circuit of claim 1, wherein said circuit is a programmable linear voltage regulator circuit.

6. The circuit of claim 1, wherein said circuit further comprises a processor, that is not the processing element, coupled with the variable voltage generator.

7. The circuit of claim 1, further comprising a programmable supervisor module coupled with said processor, wherein said nonvolatile memory is coupled with a programming interface to receive said programming and wherein said programming changes the value of a previously programmed output voltage for said variable voltage generator.

8. A circuit comprising:

a variable voltage generator coupled to receive a voltage supply, wherein the variable voltage generator comprises a follower circuit, and wherein the follower circuit comprises an amplifier coupled with a switching element;

a supervisor subsystem;

a processing element coupled to said variable voltage generator, said processing element coupled to receive programming for controlling an output voltage of said variable voltage generator; and

a non-volatile memory coupled to said processing element, said non-volatile memory to store said programming.

9. The circuit of claim 8, where said programming sets an output voltage for said circuit.

10. The circuit of claim 8, wherein said programming changes the value of a previously programmed output voltage for said variable voltage generator.

11. The circuit of claim 8, wherein said processing element can be used for generating a reset signal that is output by said circuit.

13. The circuit of claim 8, wherein the follower circuit is coupled to receive said voltage supply.

14. The circuit of claim 8, wherein said follower circuit comprises a transistor and an operational amplifier that are coupled together.

12. A circuit comprising:

a variable voltage generator coupled to receive a voltage supply, wherein the variable voltage generator comprises a follower circuit, and wherein the follower circuit comprises an amplifier coupled with a switching element;

a supervisor subsystem; and

a processing element coupled to said variable voltage generator, said processing element coupled to receive programming for controlling an output voltage of said variable voltage generator; and

wherein said variable voltage generator further comprises a first resistor ladder and a first multiplexer, wherein said supervisor subsystem comprises a second resistor ladder and a second multiplexer, and wherein said processing element can be used for disabling an output voltage of said circuit when said voltage supply crosses a threshold.

15. A method comprising:

receiving an input voltage;

receiving a reference voltage;

storing data with non-volatile memory; and

with a processing element coupled to said non-volatile memory and a variable voltage generator, utilizing said input voltage and said reference voltage to generate a regulated output voltage having a value set by said data stored by said non-volatile memory; and

regulating the regulated output voltage using a follower circuit, wherein the follower circuit comprises an amplifier coupled with a switching element.

16. The method of claim 15, wherein said regulated output voltage is output by a programmable voltage regulator circuit.

17. The method of claim 15, wherein said value is related to said reference voltage.

18. The method of claim 15, further comprising:

receiving said data via a programming interface.

19. The method of claim 15, further comprising:

receiving said data via a communication bus.