Amplifier

• US 8,072,269 B2
• Filed: 10/01/2010
• Issued: 12/06/2011
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Wu, Honglei, Xu, Yong-Ping
• Primary Examiner(s): Nguyen, Patricia
• Application Number:
  US12/896,661
• Publication Number:
  US 20110074616A1
• Time in Patent Office: 431 Days
• Field of Search: 330/253, 330/260, 330/258
• US Class Current: 330/253
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 3/45201 Non-folded cascode stages
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45672 Controlling the common source circuit of the differential amplifier

Abstract

Briefly, one or more embodiments of an amplifier, including example applications, are described.

Claims

1. An apparatus for amplifying a differential voltage signal, comprising:

an amplifier configured to remove a DC voltage signal component from the differential voltage signal to provide an analog output voltage signal; and

a successive approximation analog-to-digital converter (ADC) coupled to an output of the amplifier and configured to convert the analog output voltage signal to a digital signal;

further comprising an oscillator to provide a clock signal, wherein the oscillator is coupled to be turned on if the ADC is active and turned off otherwise.

2. The apparatus of claim 1, wherein the ADC comprises an 11 bit ADC.

3. The apparatus of claim 1, wherein the IC is adapted to operate with a one volt power source.

15. The apparatus of claim 1, wherein the apparatus is a battery operated electronic device.

16. The apparatus of claim 1, wherein the amplifier and the ADC are incorporated into an integrated circuit chip.

17. The apparatus of claim 1, wherein the apparatus is a medical device.

18. The apparatus of claim 17, wherein the medical device is an electroencephalogram or an electrocardiogram.

19. The apparatus of claim 1, wherein the apparatus is a low noise operational transconductance amplifier (LN-OTA).

20. The apparatus of claim 19, further comprising:

an input unit configured to receive signals;

an output unit configured to output signals; and

a battery configured to power the LN-OTA.

4. An apparatus for amplifying a differential voltage signal, comprising:

an amplifier configured to remove a DC voltage signal component from the differential voltage signal to provide an analog output voltage signal; and

a successive approximation analog-to-digital converter (ADC) coupled to an output of the amplifier and configured to convert the analog output voltage signal to a digital signal;

wherein the amplifier includes a DC rejection circuit implemented using at least one pseudo-resistor.

5. An apparatus for amplifying a differential voltage signal, comprising:

an amplifier configured to remove a DC voltage signal component from the differential voltage signal to provide an analog output voltage signal; and

a successive approximation analog-to-digital converter (ADC) coupled to an output of the amplifier and configured to convert the analog output voltage signal to a digital signal;

wherein the amplifier and the ADC are coupled so as to provide a pseudo-sample and hold circuit.

6. An apparatus for amplifying a differential voltage signal, comprising:

an amplifier configured to remove a DC voltage signal component from the differential voltage signal to provide an analog output voltage signal, wherein the amplifier comprises;

an input stage comprising a series-shunt feedback loop for controlling respective gate voltages of a first pair of transistors of the input stage; and

an output stage coupled to the first pair of transistors of the input stage such that respective gates of a first pair of transistors of the output stage are coupled to the respective gates of the first pair of transistors of the input stage; and

a successive approximation analog-to-digital converter (ADC) coupled to an output of the amplifier and configured to convert the analog output voltage signal to a digital signal.

7. The apparatus of claim 6, wherein the output stage is configured to provide a substantially rail-to-rail analog output voltage signal without significantly increasing noise in the analog output voltage signal.

8. The apparatus of claim 7, wherein the input stage comprises a second pair of transistors, wherein gates of the second pair of transistors of the input stage are coupled to receive the differential voltage signal, and wherein sources of the second pair of transistors of the input stage are coupled to respective drains of the first pair of transistors of the input stage.

9. The apparatus of claim 8, wherein the feedback loop comprises a resistor coupled between the sources of the second pair of transistors of the input stage.

10. The apparatus of claim 9, wherein the feedback loop further comprises a third pair of transistors in a cascade configuration with the second pair of transistors of the input stage.

11. The apparatus of claim 6, wherein the output stage comprises a second pair of transistors forming a common-mode load for the first pair of transistors of the output stage.

12. The apparatus of claim 11, further comprising a common-mode feedback circuit coupled to gates of the second pair of transistors of the output stage.

13. The apparatus of claim 12, further comprising a resistor coupled between the drains of the second pair of transistors of the output stage, wherein the common-mode feedback circuit is configured to sense a voltage at the resistor.

14. The apparatus of claim 6, further comprising a DC rejection circuit coupled to the output stage.

21. A method comprising:

amplifying a differential voltage signal including rejecting a DC component to provide an analog output voltage signal;

converting the analog output voltage signal to a digital signal by successive approximation; and

turning on an oscillator to provide a clock signal, and turning off the oscillator if said converting stops.

22. The method of claim 21, further comprising providing a substantially rail-to-rail analog output voltage signal from a one volt power source without significantly increasing noise in the analog output voltage signal.

23. A method comprising:

amplifying a differential voltage signal including rejecting a DC component to provide an analog output voltage signal;

converting the analog output voltage signal to a digital signal by successive approximation; and

sampling and holding the analog output voltage signal to initiate said converting.