LCD with common voltage driving circuits

• US 8,072,409 B2
• Filed: 02/25/2009
• Issued: 12/06/2011
• Est. Priority Date: 02/25/2009
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Fanchiang, Kuohao, Chan, Kung-Yi, Li, Huan-Hsin
• Primary Examiner(s): Nguyen, Kevin M
• Assistant Examiner(s): Ghafari, Sepideh
• Application Number:
  US12/392,796
• Publication Number:
  US 20100214204A1
• Time in Patent Office: 1,014 Days
• Field of Search: 345/98, 345/100, 345/205, 345/209
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

An LCD with power consumption reduction and a method of driving the same. In one embodiment, the LCD has a plurality of pixels spatially arranged in the form of a matrix having N pixel rows, each pixel row defined between two neighboring scanning lines G_n and G_n+1, and having an auxiliary common electrode, and a plurality of common voltage driving circuits, each common voltage driving circuit electrically coupled between the scanning line G_n and the corresponding auxiliary common electrode for providing a two-level lift-up coupling voltage to the auxiliary common electrode.

Claims

1. A liquid crystal display (LCD), comprising:

(a) a common electrode;

(b) a plurality of scanning lines, {G_n}, n=1, 2, . . . , N, N being an integer greater than zero, spatially arranged along a row direction;

(c) a plurality of data lines, {D_m}, m=1, 2, . . . , M, M being an integer greater than zero, spatially arranged crossing the plurality of scanning lines {G_n} along a column direction perpendicular to the row direction;

(d) a plurality of pixels, {P_n,m}, spatially arranged in the form of a matrix, each pixel row, defined between two neighboring scanning lines G_n and G_n+1, having an auxiliary common electrode ACE_n, each pixel P_n,m, defined between two neighboring scanning lines G_n and G_n+1 and two neighboring data lines D_m and D_m+1, comprising;

(i) a pixel electrode;

(ii) a transistor, T0, having a gate, a source and a drain electrically coupled to the scanning line G_n, the data line D_m and the pixel electrode, respectively;

(iii) a liquid crystal capacitor, Clc, electrically coupled between the pixel electrode and the common electrode; and

(iv) a charge storage capacitor, Cst, electrically coupled between the pixel electrode and the auxiliary common electrode ACE_n, and

(e) a plurality of common voltage driving circuits {CT_n}, each common voltage driving circuit CT_n, electrically coupled between the scanning line G_n and the corresponding auxiliary common electrode ACE_n, comprising;

a first transistor, T1, a second transistor, T2, a third transistor, T3, and a fourth transistor, T4, each transistor having a gate, a source and a drain, wherein the gate of each of the first transistor T1, the second transistor T2 and the third transistor T3 is electrically coupled to the gate scanning line G_n, and the gate of the fourth transistor T4 is electrically coupled to a fourth voltage, SWC_n, that is inverse to a corresponding scanning signal, g_n to be applied to the gate scanning line G_n.

2. The LCD of claim 1, wherein each common voltage driving circuit CT_n further comprises a first capacitor, C1, having a first terminal electrically coupled to the drain of the first transistor T1 and a second terminal electrically coupled to the drain of the second transistor T2 and a second capacitor, C2, having a first terminal electrically coupled to the drain of the third transistor T3 and a second terminal configured to receive a fifth voltage, VAC_n, wherein

(a) the source of the first transistor T1 is configured to receive a first voltage, VDC, and the drain of the first transistor T1 is electrically coupled to the auxiliary common electrode ACE_n;

(b) the source of the second transistor T2 is configured to receive a second voltage, VDC1_n;

(c) the source of the third transistor T3 is configured to receive a third voltage, VDC2_n; and

(d) the source of the fourth transistor T4 is electrically coupled to the drain of the third transistor T3, and the drain of the fourth transistor T4 is electrically coupled to the drain of the second transistor T2.

3. The LCD of claim 1, further comprising:

(a) a gate driver for generating a plurality of scanning signals, {g_n}, respectively applied to the plurality of scanning lines {G_n}, wherein the plurality of scanning signals {g_n} is configured to turn on the transistors T0 connected to the plurality of scanning lines {G_n} in a predefined sequence; and

(b) a data driver for generating a plurality of data signals, {d_m}, respectively applied to the plurality of data lines {D_m}.

4. The LCD of claim 3, wherein each of the plurality of scanning signals {g_n} is configured to have a waveform having a first voltage potential, V_GH, and a second voltage potential, V_GL, wherein V_GH>

V_GL, and wherein the waveform of each scanning signal g_n is sequentially shifted from one another.

5. The LCD of claim 4, wherein each of the first voltage VDC, the second voltage VDC1_n and the third voltage VDC2_n is a DC voltage, and wherein each of the fourth voltage SWC_n and the fifth voltage VAC_n is an AC voltage.

6. The LCD of claim 5, wherein VDC1_n=VDC2_n+1, and VDC2_n=VDC1_n+1, and wherein the fourth voltage SWC_n is characterized with a waveform that is complimentary to the waveform of a corresponding gate signal g_n.

7. The LCD of claim 6, wherein, in operation, the plurality of pixels {P_n,m} has a pixel polarity that is in the row inversion.

8. The LCD of claim 1, further comprising a panel having an active area for display and a non-active area adjacent to the active area, wherein the plurality of pixels, {P_n,m} is formed in the active area of the panel, and wherein the plurality of common voltage driving circuits {CT_n} is formed in the non-active area of the panel.

9. A liquid crystal display (LCD) having a plurality of scanning lines, {G_n}, spatially arranged along a row direction, and a plurality of data lines, {D_m}, spatially arranged crossing the plurality of scanning lines {G_n} along a column direction perpendicular to the row direction, n=1, 2, . . . , N, m=1, 2, . . . , M, and N, M being an integer greater than zero, comprising:

(a) a common electrode;

(b) a plurality of pixels, {P_n,m}, spatially arranged in the form of a matrix having N pixel rows and M pixel columns, each pixel row, defined between two neighboring scanning lines G_n and G<sub>n−

1</sub> having an auxiliary common electrode ACE_n, each pixel P_n,m, defined between two neighboring scanning lines G_n and G_n+1 and two neighboring data lines D_m and D_m+1, comprising;

(i) a pixel electrode;

(ii) a transistor, T0, having a gate, a source and a drain electrically coupled to the scanning line G_n, the data line D_m and the pixel electrode, respectively;

(iii) a liquid crystal capacitor, Clc, electrically coupled between the pixel electrode and the common electrode 130; and

(iv) a charge storage capacitor, Cst, electrically coupled between the pixel electrode and the auxiliary common electrode ACE_n; and

(c) a plurality of common voltage driving circuits {CT_n}, each common voltage driving circuit CT_n, electrically coupled between the scanning line G_n and the corresponding auxiliary common electrode ACE_n for providing a two-level lift-up coupling voltage to the auxiliary common electrode ACE_n.

10. The LCD of claim 9, wherein each common voltage driving circuit CT_n comprises:

(a) a first transistor, T1, having a gate electrically coupled to the scanning line G_n, a source configured to receive a first voltage, VDC, and a drain electrically coupled to the auxiliary common electrode ACE_n;

(b) a second transistor, T2, having a gate electrically coupled to the scanning line G_n, a source configured to receive a second voltage, VDC1_n, and a drain;

(c) a third transistor, T3, having a gate electrically coupled to the scanning line G_n, a source configured to receive a third voltage, VDC2_n, and a drain;

(d) a fourth transistor, T4, having a gate configured to receive a fourth voltage, SWC_n, a source electrically coupled to the drain of the third transistor T3, and a drain electrically coupled to the drain of the second transistor T2;

(e) a first capacitor, C1, having a first terminal electrically coupled to the drain of the first transistor T1 and a second terminal electrically coupled to the drain of the second transistor T2; and

(f) a second capacitor, C2, having a first terminal electrically coupled to the drain of the third transistor T3 and a second terminal configured to receive a fifth voltage, VAC_n.

11. The LCD of claim 10, further comprising:

(a) a gate driver for generating a plurality of scanning signals, {g_n}, respectively applied to the plurality of scanning lines {G_n}, wherein the plurality of scanning signals {g_n} is configured to turn on the transistors T0 connected to the plurality of scanning lines {G_n} in a predefined sequence; and

(b) a data driver for generating a plurality of data signals, {d_m}, respectively applied to the plurality of data lines {D_m}.

12. The LCD of claim 11, wherein each of the plurality of scanning signals {g_n} is configured to have a waveform having a first voltage potential, V_GH, and a second voltage potential, V_GL, wherein V_GH>

V_GL, and wherein the waveform of each scanning signal g_n is sequentially shifted from one another.

13. The LCD of claim 12, wherein each of the first voltage VDC, the second voltage VDC1_n and the third voltage VDC2_n is a DC voltage, and wherein each of the fourth voltage SWC_n and the fifth voltage VAC_n is an AC voltage.

14. The LCD of claim 13, wherein VDC1_n=VDC2_n+1, and VDC2_n=VDC1_n+1, and wherein the fourth voltage SWC_n is characterized with a waveform that is complimentary to the waveform of a corresponding gate signal g_n.

15. The LCD of claim 9, further comprising a panel having an active area for display and a non-active area adjacent to the active area, wherein the plurality of pixels, {P_n,m} is formed in the active area of the panel, and wherein the plurality of common voltage driving circuits {CT_n} is formed in the non-active area of the panel.

16. A method of driving a liquid crystal display (LCD) having a plurality of scanning lines, {G_n}, spatially arranged along a row direction, and a plurality of data lines, {D_m}, spatially arranged crossing the plurality of scanning lines {G_n} along a column direction perpendicular to the row direction, n=1, 2, . . . , N, m=1, 2, . . . , M, and N, M being an integer greater than zero, and a plurality of pixels, {P_n,m}, spatially arranged in the form of a matrix having N pixel rows and M pixel columns, each pixel row, defined between two neighboring scanning lines G_n and G₊₁, having an auxiliary common electrode ACE_n, each pixel P_n,m, defined between two neighboring scanning lines G_n and G_n+1 and two neighboring data lines D_m and D_m+1, comprising a pixel electrode, a common electrode, a transistor, T0, having a gate, a source and a drain electrically coupled to the scanning line G_n, the data line D_m and the pixel electrode, respectively, a liquid crystal capacitor, Clc, electrically coupled between the pixel electrode and the common electrode, and a charge storage capacitor, Cst, electrically coupled between the pixel electrode and the auxiliary common electrode ACE_n;

comprising the steps of;

(a) providing a plurality of common voltage driving circuits {CT_n}, each common voltage driving circuit CT_n, electrically coupled between the scanning line G_n and the corresponding auxiliary common electrode ACE_n;

(b) applying a plurality of scanning signals, {g_n}, to the plurality of scanning lines {G_n} and a plurality of data signals, {d_m}, to the plurality of data lines {D_m}, respectively, the plurality of scanning signals {g_n} configured to turn on the transistors T0 connected to the plurality of scanning lines {G_n} in a predefined sequence; and

(c) applying a plurality of common voltage driving signals to the plurality of common voltage driving circuits {CT_n} so as to responsively generate a plurality of two-level lift-up coupling voltages, each two-level lift-up coupling voltage applied to the auxiliary common electrode ACE_n of a corresponding pixel row.

17. The method of claim 16, wherein each common voltage driving signal comprises a set of a first voltage, VDC, a second voltage, VDC1_n, a third voltage, VDC2_n, a fourth voltage, SWC_n, and a fifth voltage, VAC_n.

18. The method of claim 17, wherein each common voltage driving circuit comprises:

(a) a first transistor, T1, having a gate electrically coupled to the scanning line G_n, a source configured to receive the first voltage VDC, and a drain electrically coupled to the auxiliary common electrode ACE_n;

(b) a second transistor, T2, having a gate electrically coupled to the scanning line G_n, a source configured to receive the second voltage VDC1_n, and a drain;

(c) a third transistor, T3, having a gate electrically coupled to the scanning line G_n, a source configured to receive the third voltage VDC2_n, and a drain;

(d) a fourth transistor, T4, having a gate configured to receive the fourth voltage, SWC_n, a source electrically coupled to the drain of the third transistor T3, and a drain electrically coupled to the drain of the second transistor T2;

(e) a first capacitor, C1, having a first terminal electrically coupled to the drain of the first transistor T1 and a second terminal electrically coupled to the drain of the second transistor T2; and

(f) a second capacitor, C2, having a first terminal electrically coupled to the drain of the third transistor T3 and a second terminal configured to receive the fifth voltage, VAC_n.

19. The method of claim 18, wherein each of the first voltage VDC, the second voltage VDC1_n and the third voltage VDC2_n is a DC voltage, and wherein each of the fourth voltage SWC_n and the fifth voltage VAC_n is an AC voltage.

20. The method of claim 19, wherein VDC1_n=VDC2_n+1, and VDC2_n=VDC1_n+1, and wherein the fourth voltage SWC_n is configured to have a waveform that is complimentary to a waveform of a corresponding gate signal g_n.

21. The method of claim 20, wherein, in operation, the plurality of pixels {P_n,m} has a pixel polarity that is in the row inversion.

22. A common voltage driving circuit for a liquid crystal display (LCD) having a plurality of scanning lines, {G_n}, spatially arranged along a row direction, and a plurality of data lines, {D_m}, spatially arranged crossing the plurality of scanning lines {G_n} along a column direction perpendicular to the row direction, n=1, 2, . . . , N, m=1, 2, . . . , M, and N, M being an integer greater than zero, and a plurality of pixels, {P_n,m}, spatially arranged in the form of a matrix having N pixel rows and M pixel columns, each pixel row, defined between two neighboring scanning lines G_n and G_n+1, having an auxiliary common electrode ACE_n, comprising:

(a) a first transistor, T1, having a gate electrically coupled to the scanning line G_n, a source configured to receive a first voltage, VDC, and a drain electrically coupled to the auxiliary common electrode ACE_n;

(b) a second transistor, T2, having a gate electrically coupled to the scanning line G_n, a source configured to receive a second voltage, VDC1_n, and a drain;

(c) a third transistor, T3, having a gate electrically coupled to the scanning line G_n, a source configured to receive a third voltage, VDC2_n, and a drain;

(d) a fourth transistor, T4, having a gate configured to receive a fourth voltage, SWC_n, a source electrically coupled to the drain of the third transistor T3, and a drain electrically coupled to the drain of the second transistor T2;

(e) a first capacitor, C1, having a first terminal electrically coupled to the drain of the first transistor T1 and a second terminal electrically coupled to the drain of the second transistor T2; and

(f) a second capacitor, C2, having a first terminal electrically coupled to the drain of the third transistor T3 and a second terminal configured to receive a fifth voltage, VAC_n.

23. The common voltage driving circuit of claim 22, wherein each of the first voltage VDC, the second voltage VDC1_n and the third voltage VDC2_n is a DC voltage, and wherein each of the fourth voltage SWC_n and the fifth voltage VAC_n is an AC voltage.