Semiconductor memory device that can perform successive accesses

• US 8,072,821 B2
• Filed: 11/06/2009
• Issued: 12/06/2011
• Est. Priority Date: 11/06/2008
• Status: Expired due to Fees

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Arai, Tetsuya
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Yang, Han
• Application Number:
  US12/614,129
• Publication Number:
  US 20100110803A1
• Time in Patent Office: 760 Days
• Field of Search: 365/189.04, 365/189.17, 365/189.011, 365/189.19, 365/189.05
• US Class Current: 365/189.04
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includes a write buffer that supplies the write data on the write path to the first data line, a read amplifier that supplies the read data supplied to the read path through the second data line, and a bypass circuit that supplies the write data on the write path to the read path in response to detection of matching between a write address and a read address. Thus, data collisions can be avoided.

Claims

1. A semiconductor memory device comprising:

a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word lines with the bit lines;

an input/output circuit that includes a write path to which a write data to be written in the memory cell array is supplied and a read path to which a read data read from the memory cell array is supplied; and

a first data line and a second data line that connect the input/output circuit to the memory cell array,

wherein the input/output circuit further includes;

a write buffer that supplies the write data on the write path to the first data line;

a read amplifier that supplies the read data on the second data line to the read path;

a detection circuit that detects matching between a write address that the write data is to be written to and a read address that the read data is to be read from; and

a bypass circuit that supplies the write data on the write path to the read path in response to matching detected by the detection circuit.

2. The semiconductor memory device as claimed in claim 1, wherein the input/output circuit further includes a first inhibition circuit that inhibits activation of the read amplifier in response to matching detected by the detection circuit.

3. The semiconductor memory device as claimed in claim 2, wherein the memory cell array further includes:

a plurality of sense amplifiers respectively connected to corresponding at least one of the bit lines;

a plurality of first column switches that respectively connect the bit lines to the first data line;

a plurality of second column switches that respectively connect the bit lines to the second data line;

a first column select driver that activates any one of the first column switches based on the write address;

a second column select driver that activates any one of the second column switches based on the read address; and

a second inhibition circuit that inhibits activation of the second column switch in response to matching detected by the detection circuit.

4. The semiconductor memory device as claimed in claim 1, wherein

a write operation using the first data line is performed in response to a first access request, and

a read operation using the second data line is performed in response to a second access request subsequent to the first access request.

5. The semiconductor memory device as claimed in claim 1, wherein each of the first and second data lines includes a hierarchical configuration.

6. A semiconductor memory device comprising:

a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word lines with the bit lines;

an input/output circuit that includes a first write path to which a first write data to be written in the memory cell array is supplied and a second write path to which a second write data to be written in the memory cell array is supplied; and

a first data line and a second data line that connect the input/output circuit to the memory cell array,

wherein the input/output circuit further includes;

a first write buffer that supplies the first write data on the first write path to the first data line;

a second write buffer that supplies the second write data on the second write path to the second data line;

a detection circuit that detects matching between a first write address that the first write data is to be written through the first data line and a second write address that the second write data is to be written through the second data line; and

an inhibition circuit that inhibits activation of either the first write buffer or the second write buffer in response to matching detected by the detection circuit.

7. The semiconductor memory device as claimed in claim 6, wherein the input/output circuit further includes:

a read path to which a read data read from the memory cell array is supplied;

a read amplifier that supplies the read data on the first or second data line to the read path; and

a bypass circuit that supplies the first or second write data on the first or second write path to the read path.

8. The semiconductor memory device as claimed in claim 6, wherein each of the first and second data lines includes a hierarchical configuration.