Adaptive allocation of I/O bandwidth using a configurable interconnect topology

• US 8,073,009 B2
• Filed: 07/22/2008
• Issued: 12/06/2011
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ching, Michael, Woo, Steven
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US12/177,747
• Publication Number:
  US 20080276020A1
• Time in Patent Office: 1,232 Days
• Field of Search: 370/468, 370/419, 370/463
• US Class Current: 370/468
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/18 Automatic changing of the traffic direction
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Claims

1. An integrated circuit comprising:

a plurality of contacts to connect to an electronic component via respective signal lines;

an interface having a plurality of transceivers, coupled to respective ones of the plurality of contacts, to simultaneously output to the electronic component a first number of parallel signals from a first plurality of contacts in the plurality of contacts and receive from the electronic component a second number of parallel signals on a second plurality of contacts in the plurality of contacts, the integrated circuit and the electronic component comprising a system having at least a system parameter;

bandwidth-allocation logic, coupled to the plurality of transceivers, to dynamically alter the first and second numbers responsive to at least a bandwidth-allocation control signal; and

bandwidth-allocation control logic coupled to the bandwidth-allocation logic to output the bandwidth-allocation control signal responsive to the system parameter that indicates a number of times at least one of the transceivers in the plurality of transceivers transitions between transmitting data and receiving data.

2. The integrated circuit of claim 1, wherein the interface includes at least one of a transmitter or a receiver in addition to the plurality of transceivers and coupled to a respective one of the plurality of contacts, the transmitter or receiver to convey corresponding signals in one direction, either away from or to the interface.

3. The integrated circuit of claim 1, wherein the electronic component is a memory device and the integrated circuit is a memory controller.

4. The integrated circuit of claim 3, wherein the memory device is a packaged integrated circuit memory device having a dynamic random access storage array to store data received at the interface.

5. The integrated circuit of claim 1, wherein the bandwidth-allocation logic comprises an output multiplexer to select the first number responsive to the bandwidth-allocation control signal and an input multiplexer to select the second number responsive to the bandwidth-allocation control signal.

6. The integrated circuit of claim 1, wherein the alteration of the first and second numbers comprises changing an operational mode of at least one of the transceivers to a unidirectional mode of operation.

7. A method of operation within an integrated circuit having an interface including a plurality of transceivers coupled to respective ones of a plurality of contacts that are coupled to an external electronic component, the method comprising:

outputting from a first set of contacts in the plurality of contacts a first number of parallel signals to the electronic component;

receiving, during the outputting, at a second set of contacts in the plurality of contacts a second number of parallel signals from the electronic component;

counting a number of times at least one transceiver in the plurality of transceivers transitions between outputting data and receiving data;

providing at least one control signal in response to the number of times the at least one transceiver in the plurality of transceivers transitions between outputting data and receiving data; and

altering the first and second numbers in response to the at least one control signal that indicates a bandwidth-allocation of the interface.

8. The method of claim 7, wherein the integrated circuit and the external electronic component comprise a system having at least one system parameter, and the method further comprises receiving, at the interface, the at least one control signal in response to a system parameter.

9. The method of claim 8, wherein the system parameter includes at least one of a number of transmit-receive bus turnarounds, number of transmit commands, number of receive commands, priority of data to be transferred and average time a data packet waits to be transferred.

10. The method of claim 7, wherein the altering is performed by a bandwidth-allocation logic, coupled to the plurality of transceivers, in response to the at least one control signal.

11. The method of claim 10, wherein the at least one control signal is generated by a bandwidth-allocation control logic in response to a system parameter.

12. The method of claim 7, wherein the interface includes at least a transmitter coupled to a respective one of the plurality of contacts in addition to the plurality of transceivers, further comprising:

outputting, by the transmitter, an electrical signal to the electronic component.

13. The method of claim 7 wherein the interface includes at least a receiver coupled to a respective one of the plurality of contacts in addition to the plurality of transceivers, further comprising:

receiving, by the receiver, a signal from the electronic component.

14. A system comprising:

an electronic component; and

an integrated circuit, coupled to the electronic component via a plurality of signal lines, the integrated circuit including,

a plurality of contacts coupled to respective ones of the plurality of signal lines;

an interface having a plurality of transceivers, coupled to respective ones of the plurality of contacts, to simultaneously output to the electronic component a first number of parallel signals from a first plurality of contacts in the plurality of contacts and receive from the electronic component a second number of parallel signals on a second plurality of contacts in the plurality of contacts;

bandwidth-allocation logic, coupled to the plurality of transceivers, to dynamically alter the first and second numbers responsive to at least a bandwidth-allocation control signal; and

bandwidth-allocation control logic coupled to the bandwidth-allocation logic to output the bandwidth-allocation control signal responsive to a system parameter, wherein the system parameter indicates at least a number of times at least one of the transceivers in the plurality of transceivers transitions between transmitting data and receiving data.

15. The system of claim 14, wherein the system parameter includes at least one of a number of transmit-receive bus turnarounds, number of transmit commands, number of receive commands, priority of data to be transferred and average time a data packet waits to be transferred.

16. The system of claim 14, wherein the electronic component is a memory device and the integrated circuit is a memory controller.

17. The system of claim 14, wherein the bandwidth-allocation logic alters the first and second numbers when the electronic component has data to be output as a third number of parallel signals to the integrated circuit.