Multi mode radio frequency transceiver front end circuit

• US 8,073,400 B2
• Filed: 04/22/2009
• Issued: 12/06/2011
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: RFaxis, Inc. (Skyworks Solutions Incorporated)
• Inventors: Gorbachov, Oleksandr
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Englund, Terry L
• Application Number:
  US12/428,409
• Publication Number:
  US 20100210299A1
• Time in Patent Office: 958 Days
• Field of Search: None
• US Class Current: 455/83
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

A front end circuit for coupling an antenna to a first radio frequency (RF) transceiver and a second RF transceiver is contemplated. The RF transceivers have a signal input, a signal output, a receive enable line and a transmit enable line. In addition to an antenna port, the front end circuit has a first power amplifier and a first low noise amplifier both coupled to first RF transceiver, and a second power amplifier and a second low noise amplifier both coupled to the second RF transceiver. The front end circuit includes a matching network that couples the power amplifiers and the low noise amplifiers, the various outputs and inputs thereof being common.

Claims

1. A front end circuit for radio frequency transceivers having a predefined operating frequency for connecting the transceivers to an antenna, the front end circuit comprising:

an antenna port connectable to the antenna;

a first transmit port associated with a first one of the transceivers;

a first receive port associated with the first one of the transceivers;

a shared transmit and receive port associated with a second one of the transceivers;

a first power amplifier including a first power amplifier transistor having a base coupled to the first transmit port, a collector, and an emitter;

a second power amplifier including a second power amplifier transistor having a base coupled to the shared transmit and receive port, a collector and an emitter;

a first low noise amplifier including a first cascode transistor having a base, a collector, and an emitter;

a second low noise amplifier including a second cascode transistor having a base, a collector, and an emitter;

a low noise amplifier transistor having a base, an emitter, and a collector coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor; and

a matching circuit including a power amplifier output matching segment coupled to the collector of the first power amplifier transistor and the collector of the second power amplifier transistor, and a low noise amplifier input matching segment coupled to the base of the low noise amplifier transistor, the power amplifier output matching segment having shared components with the low noise amplifier input matching segment.

2. The front end circuit of claim 1, further comprising:

a first power amplifier input matching network coupling the first transmit port and the base of the first power amplifier transistor; and

a first low noise amplifier output matching network coupling the collector of the first cascode transistor to the first receive port.

3. The front end circuit of claim 2, further comprising:

a second power amplifier input matching network coupling the shared transmit and receive port and the base of the second power amplifier transistor; and

a second low noise amplifier output matching network coupling the collector of the second cascade transistor to the shared transmit and receive port;

wherein the second low noise amplifier output matching network is chained with the second power amplifier input matching network, an output impedance thereon being matched with the second one of the transceivers.

4. The front end circuit of claim 3, wherein:

the second power amplifier input matching network defines a first network segment, a second network segment, and a shared network segment, a junction between the first network segment and the second network segment defining a common point;

the second low noise amplifier output matching network defines a third network segment and the shared network segment; and

the second low noise amplifier output matching network is connected to the common point.

5. The front end circuit of claim 4, wherein an impedance of the first network segment of the second power amplifier input matching network is substantially equivalent to an impedance of the third network segment of the second low noise amplifier output matching network.

6. The front end circuit of claim 4, wherein the shared network segment further includes an electrostatic discharge inductor coupled to the shared transmit and receive port.

7. The front end circuit of claim 1, further comprising:

a first power amplifier control circuit with a first adjustable voltage source coupled to the base of the first power amplifier transistor, the first power amplifier control circuit activating and setting a bias point of the first power amplifier transistor; and

a second power amplifier control circuit with a second adjustable voltage source coupled to the base of the second power amplifier transistor, the second power amplifier control circuit activating and setting a bias point of the second power amplifier transistor.

8. The front end circuit of claim 7, further comprising:

a first low noise amplifier control circuit with a third adjustable voltage source coupled to the first cascode transistor, the first low noise amplifier control circuit activating and setting a bias point of the first cascode transistor;

a second low noise amplifier control circuit with a fourth adjustable voltage source coupled to the second cascode transistor, the second low noise amplifier control circuit activating and setting a bias point of the second cascode transistor; and

a shared low noise amplifier control circuit with the third adjustable voltage source and the fourth adjustable voltage source coupled to the low noise amplifier transistor, the shared low noise amplifier control circuit activating and setting a bias point of the low noise amplifier transistor.

9. The front end circuit of claim 8, wherein the shared low noise amplifier control circuit further includes a resistive divider having a resistance value greater than an active base-emitter resistance of the low noise amplifier transistor.

10. The front end circuit of claim 8, wherein at least one of the first power amplifier control circuit, the second power amplifier control circuit, the first low noise amplifier control circuit, and the second low noise amplifier control circuit is based upon a voltage supply.

11. The front end circuit of claim 8, wherein at least one of the first power amplifier control circuit, the second power amplifier control circuit, the first low noise amplifier control circuit, and the second low noise amplifier control circuit has a current mirror architecture.

12. The front end circuit of claim 1, wherein the low noise amplifier transistor has a common-emitter configuration.

13. The front end circuit of claim 1, wherein the matching circuit includes a series resonance element coupled to ground resonating at a second harmonic of the operating frequency.

14. The front end circuit of claim 1, further comprising:

a degeneration inductor coupled to the emitter of the low noise amplifier transistor.

15. The front end circuit of claim 1, wherein:

the first power amplifier has a plurality of amplification stages, the first power amplifier transistor corresponding to a first amplification stage of the first power amplifier, and another power amplifier transistor corresponding to a second amplification stage of the first power amplifier; and

the second power amplifier has a plurality of amplification stages, the second power amplifier transistor corresponding to a first amplification stage of the second power amplifier, and another power amplifier transistor corresponding to a second amplification stage of the second power amplifier.

16. The front end circuit of claim 1, wherein:

the first low noise amplifier has a plurality of amplification stages, the first cascode transistor corresponding to a first amplification stage of the first low noise amplifier, and another low noise amplifier transistor corresponding to a second amplification stage of the first low noise amplifier; and

the second low noise amplifier has a plurality of amplification stages, the second cascode transistor corresponding to a first amplification stage of the second low noise amplifier, and another low noise amplifier transistor corresponding to a second amplification stage of the second low noise amplifier.

17. The front end circuit of claim 1, wherein the first power amplifier transistor, the second power amplifier transistor, the first cascode transistor, the second cascode transistor, and the low noise amplifier transistor have a transistor structure selected from the group consisting of:

bipolar junction and hetero-junction bipolar.

18. The front end circuit of claim 1, wherein:

the first power amplifier transistor, the second power amplifier transistor, the first cascode transistor, the second cascode transistor, and the low noise amplifier transistor have a transistor structure selected from the group consisting of;

metal semiconductor field effect, metal oxide semiconductor field effect, and high electron mobility;

the respective one of the collectors of the transistors corresponding to drains;

the respective one of the emitters of the transistors corresponding to sources; and

the respective one of the bases of the transistors corresponding to gates.