Programmable heterogeneous memory controllers for main memory with different memory modules

• US 8,074,022 B2
• Filed: 09/28/2007
• Issued: 12/06/2011
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Okin, Kenneth Alan, Moussa, George, Ganapathy, Kumar, Karamcheti, Vijay, Parekh, Rajesh
• Primary Examiner(s): Bataille, Pierre-Michel
• Assistant Examiner(s): Fishburn, John P
• Application Number:
  US11/864,860
• Publication Number:
  US 20080082751A1
• Time in Patent Office: 1,530 Days
• Field of Search: None
• US Class Current: 711/115
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Claims

1. A programmable heterogeneous memory controller comprising:

a system interface to couple to a processor, the system interface to provide access of a main memory to the processor;

a flexible memory channel interface with reconfigurable pins of one or more flexible input/output (I/O) ports, the flexible memory channel interface to couple to memory modules of mixed types in sockets of one or more respective memory channels; and

one or more input/output (I/O) state machines coupled between the system interface and the flexible memory channel interface, the one or more I/O state machines to program pin configurations and generate logic signals for one or more of the reconfigurable pins of the flexible memory channel interface in response to the type of memory module being accessed in a given socket and its respective memory module software driver.

2. The programmable heterogeneous memory controller of claim 1, wherein each respective memory module software driver includes memory type, pin configuration, signal timing, and signal logic levels associated with a memory module identification of a memory module.

3. The programmable heterogeneous memory controller of claim 1, further comprising:

an input/output (I/O) buffer coupled between the system interface and the one or more I/O state machines, the I/O buffer to buffer addresses, controls, and data received from a processor for the I/O state machine and to buffer data from the I/O state machine to be written out to a processor.

4. The programmable heterogeneous memory controller of claim 1, further comprising:

a flexible port controller coupled between the I/O state machine and the flexible memory channel interface, the flexible port controller to select the functionality of each of the reconfigurable pins of the one or more flexible input/output (I/O) ports in response to a pin configuration.

5. The programmable heterogeneous memory controller of claim 1, further comprising:

a memory module socket register coupled to the I/O state machine, the memory module socket register to store the memory module identification (ID) of each memory module plugged into each socket in each memory channel;

a micro-coded memory coupled to the memory module socket register, the micro-coded memory to store the memory module software drivers for each different type of memory module indicated by the memory module socket register and supply memory module software drivers to the I/O state machine.

6. The programmable heterogeneous memory controller of claim 1, wherein

each of the one or more input/output (I/O) state machines include a memory channel state machine for each memory channel coupled to the programmable heterogeneous memory controller, each memory channel state machine includes

one or more memory module state machines for each memory module and each rank of memory therein, wherein to read and write data over the memory channel bus into each memory module coupled thereto, the one or more memory module state machines

configure the flexible memory channel interface with an appropriate pin-out in response to the type of memory module being accessed,

generate appropriate logic levels of signals in response to the type of memory module being accessed, and

read and generate signals on a memory channel bus at the appropriate time in response to the type of memory module being accessed;

a controller coupled to the one or more memory module state machines, the controller to control which one of the one or more memory module state machines is active; and

a bus arbiter coupled to the controller and the one or more memory module state machines, the bus arbiter to arbitrate access by the one or more memory module state machines to the memory channel bus.

7. The programmable heterogeneous memory controller of claim 6, wherein

the controller further controls what operational mode the one or more memory module state machines are operating in response to the type of memory access requested and the location in the memory channel of the memory module being accessed.

8. The programmable heterogeneous memory controller of claim 7, wherein

the operational mode includes a read access operation, a write access operation, and an initialization/erasure operation.

9. The programmable heterogeneous memory controller of claim 7, wherein

the location of the memory module is the socket into which the memory module is coupled.