System and method for assigning tags to control instruction processing in a superscalar processor

• US 8,074,052 B2
• Filed: 09/15/2008
• Issued: 12/06/2011
• Est. Priority Date: 12/31/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Iadonato, Kevin R., Deosaran, Trevor A., Garg, Sanjiv
• Primary Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US12/210,738
• Publication Number:
  US 20090013158A1
• Time in Patent Office: 1,177 Days
• Field of Search: 712/23, 712/216, 712/215, 716/3, 716/18
• US Class Current: 712/23
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for tagging instructions. A register file stores information required for the execution of each instruction at a location in the register file defined by the tag assigned to that instruction. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

Claims

1. A non-transitory computer-readable storage medium having instructions stored thereon, the instructions being configured when executed to design a system configured to track instructions in a variable advance instruction window, the instructions comprising:

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with an instruction source of the system, the instruction source being configured to provide a plurality of items of instruction information, wherein each of the plurality of items of instruction information pertain to an instruction to be executed;

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with a plurality of register files of the system, the plurality of register files being coupled to the instruction source; and

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with control logic of the system, the control logic being configured to couple the instruction source and the plurality of register files, the control logic adapted to selectively route each of the plurality of information items for storage in one or more of the plurality of register files, wherein each of the plurality of register files stores at least one of the plurality of items of instruction information and wherein each of the plurality of items of instruction information is stored in a location in a register file that is uniquely addressable by a unique identifier assigned to the instruction to be executed.

2. The non-transitory computer-readable storage medium of claim 1, wherein the instruction source comprises an instruction decoder.

3. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes decoded information pertaining to the instruction to be executed.

4. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes functional unit requirements for the instruction to be executed.

5. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes a type of operation to be performed by the instruction to be executed.

6. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes information specifying a storage location at which a result of the instruction to be executed is to be stored.

7. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes information specifying a storage location at which an operand of the instruction to be executed is stored.

8. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes information specifying a target address of the instruction to be executed.

9. The non-transitory computer-readable storage medium of claim 1, wherein the plurality of items of instruction information includes information specifying immediate data to be used in an operation specified by the instruction to be executed.

10. The non-transitory computer-readable storage medium of claim 1, wherein the control logic is further adapted to store the unique identifier assigned to the instruction to be executed in a slot in a recycling queue, wherein the recycling queue comprises a plurality of slots equal in number to a predetermined number of storage locations in each of the plurality of register files.

11. A non-transitory computer-readable storage medium that includes instructions configured when executed to generate a model of a system configured to control instruction processing in a superscaler processor, the instructions comprising:

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with an instruction source in the system, the instruction source configured to supply instructions to be executed by the superscaler processor;

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with a register file in the system, the register file comprising a plurality of buffer locations and a plurality of output ports; and

a storage medium instruction embodied in a behavioral description, the instruction converting the behavioral description to a chip design with a queue in the system, the queue comprising a plurality of slots, each of said plurality of slots storing a tag, wherein each tag stored in said queue identifies a unique one of said plurality of buffer locations,

wherein each instruction supplied by said instruction store is associated with one of said tags until said instruction retires, and

wherein at least a part of said instruction is stored in the buffer location identified by the tag to which said instruction is associated.

12. The non-transitory computer-readable storage medium of claim 11, wherein each of said plurality of output ports is associated with a unique one of said slots of said queue, such that the output of any one of said output ports is the item stored in the buffer location identified by the tag that is stored in the slot associated with said any one of said output ports.

13. The non-transitory computer-readable storage medium of claim 11, wherein said queue comprises four slots.

14. The non-transitory computer-readable storage medium of claim 13, wherein said register file comprises four output ports.

15. The non-transitory computer-readable medium of claim 11, wherein the number of output ports of said register file is equal to the number of slots of said queue.

16. The non-transitory computer-readable storage medium of claim 11, wherein said queue is a recycling queue.

17. The non-transitory computer-readable storage medium of claim 16, wherein if an instruction retires each of said tags in said queue, except a tag in a top slot of said queue, moves up one slot, and said tag in said top slot of said queue moves to a bottom slot of said queue.

18. The non-transitory computer-readable storage medium of claim 16, wherein if an instruction retires each of said tags in said queue, except a tag in a bottom slot of said queue, moves down one slot, and said tag in said bottom slot of said queue moves to a top slot of said queue.