Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code

• US 8,074,055 B1
• Filed: 08/30/1999
• Issued: 12/06/2011
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Van Dyke, Korbin S., Ramesh, Tiruvur R., Hohensee, Paul H., Yates, Jr., John S., Reese, David L.
• Primary Examiner(s): ELLIS, RICHARD L
• Application Number:
  US09/385,394
• Time in Patent Office: 4,481 Days
• Field of Search: 719/321, 712/43, 712/227, 712/229, 712/209
• US Class Current: 712/43
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding

Abstract

A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction'"'"'s page.

Claims

1. A method, comprising:

executing instructions fetched from first and second regions of a memory of a computer, the instructions of the first and second regions being coded for execution by computers of first and second instruction set architectures or following first and second data storage conventions, respectively, the memory regions having associated first and second indicator elements, the indicator elements each having a value indicating the architecture or data storage convention under which instructions from the associated region are to be executed, the first architecture having a pre-defined, established definition, the computer providing an implementation of the first architecture;

when execution of the instruction data flows or transfers from the first region to the second region, adapting the computer for execution in the second architecture or data storage convention, wherein the adapting includes controlling instruction execution hardware of the computer to interpret the instructions according to the two instruction set architectures according to the indicator elements;

recognizing when program execution has flowed or transferred from a region whose indicator element indicates the first data storage convention to a region whose indicator element indicates the second data storage convention, and in response to the recognition, altering the data storage content of the computer to create a program context under the second data storage convention that is logically equivalent to a re-alteration program context under the first data storage convention;

classifying control-flow instructions of a computer instruction set into a plurality of classes;

during execution of a program on the computer as part of the execution of instructions of the instruction set, updating a record of the class of the classified control-flow instruction most recently executed; and

the altering process being determined, at least in part, by the instruction class record.

2. The method of claim 1, wherein:

the regions are pages managed by a virtual memory manager.

3. The method of claim 2, wherein the indicator elements are stored in a table of indicator elements distinct from a primary address translation table used by the virtual memory manager, the indicator elements of the table associated with corresponding pages of the memory.

4. The method of claim 2, wherein the indicator elements are stored in a table, each indicator element associated with a corresponding physical page frame.

5. The method of claim 2, wherein the indicator elements are stored in a table whose entries are indexed by physical page frame number.

6. The method of claim 1, wherein the regions are lines of an instruction cache.

7. The method of claim 1, wherein a mode of execution of the instructions is changed without software intervention when execution flows or transfers from the first region to the second region.

8. The method of claim 1, wherein execution of the computer takes an exception when execution flows or transfers from the first region to the second region.

9. The method of claim 8, wherein a mode of execution of the instructions is explicitly controlled by an exception handler.

10. The method of claim 1, wherein:

one of the regions stores an operating system binary coded in an instruction set non-native to the computer, the non-native instruction set providing access to a reduced subset of the resources of the computer.

11. The method of claim 1, wherein:

one of the two data storage conventions is a register-based calling convention, and the other data storage convention is a memory stack-based calling convention.

12. The method of claim 1,

wherein the instruction data coded for execution by a first of the two instruction set architectures observes a first data storage convention associated with the first architecture, and instruction data coded for execution by a second of the two instruction set architectures observes a second data storage convention associated with the second architecture, the second data storage convention being different from the first data storage convention, a single indicator element indicating both the instruction set architecture and the data storage convention;

and

further comprising recognizing when program execution flows or transfers from a region using the first instruction set architecture to a region using the second instruction set architecture, and in response to the recognition, adjusting the data storage content of the computer from the first data storage convention to the second data storage convention.

13. A method comprising:

executing instructions fetched from first and second regions of a memory of a computer, the instructions of the first and second regions being coded for execution by computers following first and second data storage conventions, the memory regions having associated first and second indicator elements, the indicator elements each having a value indicating the data storage convention under which instructions from the associated region are to be executed;

recognizing when program execution has flowed or transferred from a region whose indicator element indicates the first data storage convention to a region whose indictor element indicates the second data storage convention, and in response to the recognition, altering the data storage content of the computer to create a program context under the second data storage convention that is logically equivalent to a pre-alteration program context under the first data storage convention;

classifying control-flow instructions of a computer instruction set into a plurality of classes; and

during execution of a program on the computer, as part of the execution of instructions of the instruction set, updating a record of the class of the classified control-flow instruction most recently executed;

the altering process being determined, at least in part, by the instruction class record.

14. The method of claim 13, wherein:

one of the two data storage conventions is a register-based calling convention, and the other data storage convention is a memory stack-based calling convention.

15. The method of claim 13, wherein:

in some of the control-flow instructions, the classification is statically determined by an opcode of the instructions; and

in other of the control-flow instructions, the classification is dynamically determined based m a full/empty status of a register.

16. A computer processor, comprising:

a processor pipeline configured to alternately execute instructions of two different instruction set architectures or processing conventions; and

a memory unit designed to fetch instructions from a computer memory for execution by the pipeline, and to fetch stored indicator elements associated with respective memory regions of a single address space from which the instructions are to be fetched, each indicator element designed to store an indication of the architecture or processing convention under which the instruction data of the associated region are to be executed by the pipeline and an indication of a calling convention under which the instruction data of the associated region is coded for execution by the pipeline, the first architecture having a predefined, established definition, the computer providing an implementation of the first architecture;

the memory unit or processor pipeline further designed to recognize an execution flow or transfer from a region whose indicator element indicates one architecture or processing convention to another;

processor pipeline control circuitry designed to control the pipeline to effect interpretation of the instructions under the two instruction set architectures alternately, according to the associated indicator elements;

software programmed to manage a transition between the execution of a program executing in the first instruction set architecture, being an instruction set architecture native to the computer processor, and execution of an operating system coded in the second instruction set, being an instruction set non-native to the computer and providing access to a reduced subset of the resources of the computer;

software programmed to alter the data storage content of a computer using the computer processor to create a program context under the second calling convention that is logically equivalent to a pre-alteration program context under the first calling convention;

the memory unit further designed to recognize when program execution has flowed or transferred from a region whose indicator element indicates the first calling convention to a region whose indicator element indicates the second calling convention and in response to the recognition to invoke the transition management software;

wherein control-flow instructions of the instruction set are classified into a plurality of classes;

the pipeline updates a record of the class of the classified control-flow instruction most recently executed;

the storage alteration process being determined, at least in part, by the instruction class record.

17. The computer processor of claim 16, wherein the indicator elements are stored in a table of indicator elements distinct from a primary address translation table used by a virtual memory manager, the indicator elements of the table associated with corresponding pages of the memory.

18. The computer processor of claim 16, further comprising:

a translation look-aside buffer (TLB); and

TLB control circuitry designed to load the indicator elements into the TLB from a table stored in memory, the entries of the table being indexed by corresponding physical page frame number.

19. The computer processor of claim 16, wherein the memory unit is further designed to recognize a single indicator element to indicate both the instruction set architecture and calling convention of a region.

20. The computer processor of claim 16, wherein the memory unit and software are designed to effect a transition between instruction boundaries, between execution in a region coded in the first instruction set using the first calling convention to execution in a region coded in the second instruction set using the second calling convention, so that code at the source of the flow or transfer may effect the execution transition without being specially coded for code at the destination.

21. The computer processor of claim 16, wherein:

one of the two calling conventions is a register-based calling convention, and the other calling convention is a memory stack-based calling convention.

22. The computer processor of claim 16, wherein the logical resources for support of the first and second instruction set architectures are overlaid on the physical resources of the computer processor according to a mapping that assigns corresponding resources of the two architectures to a common physical resource when the resources serve analogous functions in the calling conventions of the two architectures.

23. The computer processor of claim 16, wherein

a rule for altering the data storage content from the first calling convention to the second calling convention is determined by examining a descriptor associated with the location of execution before the recognized execution flow or transfer.

24. The computer processor of claim 16, further comprising:

a transition manager designed to effect a transition between the execution of code coded in instructions of a first instruction set architecture and code coded in instructions of a second instruction set architecture, the transition manager designed to alter a bit representation of a datum from a first representation under the first architecture to a second representation under the second architecture, the alteration of representation being chosen to preserve the meaning of the datum across the change in execution architecture.

25. The computer processor of claim 16, further comprising:

circuitry designed to raise an exception when the computer recognizes that execution has flowed or transferred from a region whose indicator element indicates one architecture or execution convention to another.

26. A method comprising:

storing instructions in pages of a computer memory managed by a virtual memory manager, the instruction data of the pages being coded for execution by, respectively, computers of two different architectures or under first and second data storage conventions;

in association with pages of the memory, storing corresponding indicator elements indicating the architecture or convention in which the instructions of the pages are to be executed, the pages'"'"' indicator elements being stored in a table whose entries are indexed by physical page frame number;

executing instructions from the pages in a common processor, the processor designed, responsive to the page indicator elements, to execute instructions in the architecture or under the convention indicated by the indicator element corresponding to the instruction'"'"'s page;

recognizing when program execution has flowed or transferred from a region whose indicator element indicates the first data storage convention to a region whose indicator element indicates the second data storage convention, and in response to the recognition, altering the data storage content of the computer to create a program context under the second data storage convention that is logically equivalent to a pre-alteration program context under the first data storage convention;

classifying control-flow instructions of a computer instruction set into a plurality of classes; and

during execution of a program on the computer, as part of the execution of instructions of the instruction set, updating a record of the class of the classified control-flow instruction most recently executed;

the altering process being determined, at least in part, by the instruction class record.

27. A microprocessor chip, comprising:

an instruction unit, configured to fetch instructions from a memory managed by the virtual memory manager, and configured to execute instructions coded for first and second different computer architectures or coded to implement first and second different data storage conventions;

the microprocessor chip designed to;

retrieve indicator elements stored in association with respective pages of the memory, each indicator element indicating the architecture or convention in which the instructions of the page are to be executed,

recognize when instruction execution has flowed or transferred from a page of the first architecture or convention to a page of the second architecture or convention, as indicted by the respective associated indicator elements, and

alter a processing mode of the instruction unit or a storage content of the memory to effect execution of instructions in accord with the indicator element associated with the page of the second architecture or convention;

wherein the indicator elements are stored in an instruction cache distinct from a primary address translation table used by a virtual memory manager, the indicator elements of the table being stored in association with respective pages of the memory.

28. The microprocessor chip of claim 27, wherein the microprocessor chip is designed to raise an exception when execution flows or transfers from the first region to the second region;

and

further comprising an exception handler designed to handle the exception by explicitly controlling a mode of execution of the instructions.

29. The microprocessor chip of claim 27, wherein:

the two architectures are two instruction set architectures, and

the microprocessor chip controls the instruction unit to interpret the instructions according to the two instruction set architectures according to the indicator element corresponding to the pages from which the instructions are fetched.

30. The microprocessor chip of claim 29, further comprising:

software programmed to manage a transition between the execution of a program executing in the first instruction set architecture, being an instruction set architecture native to the computer processor, and execution of an operating system coded in the second instruction set, being an instruction set non-native to the computer and providing access to a reduced subset of the resources of the computer.

31. The microprocessor chip of claim 29:

wherein each indicator element is further designed to store an indication of a data storage convention under which the instruction data of the associated page is coded for execution by the instruction unit; and

further comprising software programmed to alter the data storage content of a computer using the microprocessor chip, to create a program context under the second data storage convention that is logically equivalent to a pre-alteration program context under the first data storage convention;

the microprocessor chip further designed to recognize when program execution has flowed or transferred from a region whose indicator element indicates the first data storage convention to a region whose indicator element indicates the second data storage convention, and in response to the recognition, to invoke the transition management software.

32. The microprocessor chip of claim 31, further designed to recognize a single indicator element to indicate both the instruction set architecture and calling convention of a page.

33. The microprocessor chip of claim 27, wherein control-flow instructions of the microprocessor'"'"'s instruction set are classified into a plurality of classes;

and

the instruction unit updates a record of the class of the classified control-flow instruction most recently executed;

the storage alteration process being determined, at least in part, by the instruction class record.

34. A computer processor, comprising:

a processor pipeline configured to alternately execute instructions of two different instruction set architectures; and

a memory unit designed to fetch instructions from a computer memory for execution by the pipeline, and to fetch stored indicator elements associated with respective memory regions of a single address space from which the instructions are to be fetched, each indicator element designed to store an indication of the architecture under which the instruction data of the associated region are to be executed by the pipeline, and to store a separate indicator element designed to indicate a data storage convention observed by instructions of the associated region;

the memory unit or pipeline further designed to recognize an execution flow or transfer from a region whose indicator element indicates one instruction set architecture to another;

hardware or software designed to recognize when program execution has flowed or transferred from a region whose indicator element indicates the first data storage convention to a region whose indicator element indicates the second data storage convention, and in response to the recognition, to alter the data storage content of the computer to create a program context under the second data storage convention that is logically equivalent to a pre-alteration program context under the first data storage convention, wherein the data storage convention indicator elements are designed to store an indication of a calling convention under which the instruction data of the associated region are coded for execution by the pipeline;

processor pipeline control circuitry designed to control the pipeline to effect interpretation of the instructions under the two instruction set architectures alternately, according to the associated indicator elements;

software programmed to manage a transition between the execution of a program executing in the first instruction set architecture, being an instruction set architecture native to the computer processor, and execution of an operating system coded in the second instruction set, being an instruction set non-native to the computer and providing access to a reduced subset of the resources of the computer;

software programmed to alter the data storage content of a computer using the under a second calling convention that is logically equivalent to a pre-alteration program context under a first calling convention;

the memory unit is further designed to recognize when program execution has flowed or transferred from a region whose indicator element indicates the first calling convention to a region whose indicator element indicates the second calling convention, and in response to the recognition, to invoke the transition management software;

wherein control-flow instructions of the instruction set are classified into a plurality of classes;

the pipeline updates a record of the class of the classified control-flow instruction most recently executed;

the storage alteration process being determined, at least in part, by the instruction class record.

35. The computer processor of claim 34, wherein the memory unit and software are designed to effect a transition between instruction boundaries, between execution in a region coded in the first instruction set using the first calling convention to execution in a region coded in the second instruction set using the second calling convention, so that code at the source of the flow or transfer may effect the execution transition without being specially coded for code at the destination.

36. The computer processor of claim 34, wherein:

one of the two calling conventions is a register-based calling convention, and the other calling convention is a memory stack-based calling convention.

37. The computer processor of claim 34, wherein the logical resources for support of the first and second instruction set architectures are overlaid on the physical resources of the computer processor according to a mapping that assigns corresponding resources of the two architectures to a common physical resource when the resources serve analogous functions in the calling conventions of the two architectures.

38. The computer processor of claim 34, further comprising:

a transition manager designed to effect a transition between execution under the first calling convention to execution under the second calling convention, the transition manager designed to alter a bit representation of a datum from a first representation to a second representation, the alteration of representation being chosen to preserve the meaning of the datum across the change in calling convention.

39. The computer processor of claim 34, further comprising:

software or hardware designed to copy a datum from a first location to a second location, the first location having a use under the first calling convention analogous to the use of the second location under the second calling convention.

40. The computer processor of claim 39, further comprising:

software or hardware designed to copy a datum from a third location to a fourth location, the third location having a use under the first calling convention analogous to the use of the third location under the first calling convention and to the fourth location under the second calling convention, the software or hardware for the copying being programmed to assume that exactly one of the first and third locations is no longer required by the execution of the program.

41. The computer processor of claim 34, wherein

a rule for altering the data storage content from the first calling convention to the second calling convention is determined by examining a descriptor associated with the instruction before the recognized execution flow or transfer.

42. The computer processor of claim 34, wherein:

the regions are pages managed by a virtual memory manager.

43. The computer processor of claim 34, wherein the indicator elements are stored in virtual address translation table entries.

44. The computer processor of claim 34, wherein the indicator elements are stored in a table of indicator elements distinct from a primary address translation table used by a virtual memory manager, the indicator elements of the table associated with corresponding pages of the memory.

45. The computer processor of claim 34, wherein the indicator elements are stored in respective entries of a table whose entries are indexed by physical page frame number.

46. The computer processor of claim 34, wherein:

the indicator elements are stored in storage that is architecturally addressable when the pipeline is executing in one of the architectures and architecturally unaddressable when the pipeline is executing in the other architecture.

47. The computer processor of claim 34, further comprising:

circuitry designed to raise an exception when execution flows or transfers from a region whose indicator element indicates one architecture to another.