Method for recognizing a power failure in a data memory and recovering the data memory

• US 8,074,120 B2
• Filed: 12/12/2006
• Issued: 12/06/2011
• Est. Priority Date: 12/20/2005
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Aue, Axel
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Leibovich, Yair
• Application Number:
  US12/097,324
• Publication Number:
  US 20090158089A1
• Time in Patent Office: 1,820 Days
• Field of Search: 714/15, 714/48
• US Class Current: 714/48
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

To detect a power failure in a volatile data memory containing useful data units and test data units associated with the useful data units, the associated test data unit is also read when the useful data unit is read-accessed, and a decision is made as to whether the useful data unit is corrupted based on the test data unit. A power failure is identified when at least two read useful data units within a predefined number of successive read accesses are found to be corrupted.

Claims

1. A method for detecting a power failure supplied to a volatile data memory, the volatile data memory containing memory cells, each of the memory cells including an associated parity bit, the method comprising:

reading a memory cell and associated parity bit when the memory cell is read-accessed;

deciding, based on the parity bit, whether the memory cell is corrupted; and

identifying a power failure when at least two read memory cells within a predefined number of successive read accesses are found to be corrupted,

wherein the reading processes are not performed specifically for the purpose of identifying errors or failures,

wherein the reading process is performed within a scope of carrying out a task that is different from the detecting of a power failure, and processing of the task is not delayed by the detecting, and

wherein the predefined number are chosen such that a likelihood of at least two radiation-induced corruptions of the data units is substantially low.

2. The method as recited in claim 1, wherein a memory cell found to be corrupted is corrected based on the parity bit when the finding does not result in identification of a power failure.

3. The method as recited in claim 1, further comprising:

in response to the identifying the power failure;

discarding data stored in the memory cells from at least a portion of the volatile data memory; and

recovering the memory cells from a source outside the volatile memory.

4. The method as recited in claim 3, wherein the memory cells are recovered, at least in part, by recomputation based on measured data.

5. The method as recited in claim 3, wherein the memory cells are recovered, at least in part, by transferal from a nonvolatile memory.

6. The method as recited in claim 3, wherein memory cells which have not been found to be corrupted are also recovered.

7. The method as recited in claim 3, wherein a memory cell found to be corrupted is corrected based on the parity bit when the finding does not result in identification of a power failure.

8. The method as recited in claim 3, wherein the memory cells are recovered, at least in part, by at least one of (i) recomputation based on measured data, and (ii) at least in part, by transferal from a nonvolatile memory, and wherein memory cells which have not been found to be corrupted are also recovered.

9. The method as recited in claim 8, wherein a memory cell found to be corrupted is corrected based on the parity bit when the finding does not result in identification of a power failure.

10. The method as recited in claim 1, wherein a memory cell found to be corrupted is corrected based on the parity bit when the finding does not result in identification of a power failure.