Backside illuminated image sensor with shallow backside trench for photodiode isolation

• US 8,076,170 B2
• Filed: 11/11/2010
• Issued: 12/13/2011
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Brady, Frederick T.
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US12/944,268
• Publication Number:
  US 20110059572A1
• Time in Patent Office: 397 Days
• Field of Search: 438/57, 438/70, 438/401, 438/455, 438/458, 438/72, 257/E21.617
• US Class Current: 438/57
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Claims

1. A wafer level processing method for forming a plurality of image sensors each having a pixel array configured for backside illumination, the image sensors being formed utilizing an image sensor wafer, the image sensor wafer comprising a substrate and a sensor layer formed over the substrate, the method comprising:

forming backside trenches in a backside surface of the sensor layer;

implanting a dopant into the sensor layer through the backside trenches so as to form backside field isolation implant regions corresponding to the backside trenches;

filling the backside trenches with a material;

forming at least one antireflective layer over the filled backside trenches;

attaching a temporary carrier wafer to the backside surface and removing the substrate; and

after removing the substrate, further processing the image sensor wafer to form the plurality of image sensors including the pixel arrays for the plurality of image sensors.

2. The method of claim 1 wherein the image sensor wafer comprises a silicon-on-insulator (SOY) wafer having a buried oxide layer arranged between the substrate and the sensor layer.

3. The method of claim 1 wherein the image sensor wafer comprises an epitaxial wafer having a P−

sensor layer formed over a P+ substrate.

4. The method of claim 1 further comprising:

forming an oxide layer over the sensor layer;

forming a nitride layer over the oxide layer;

forming alignment marks that extend through the oxide and nitride layers and into the sensor layer.

5. The method of claim 4 wherein forming backside trenches in the backside surface of the sensor layer further comprises etching the backside trenches through the nitride and oxide layers.

6. The method of claim 1 further comprising forming a liner oxide layer within the backside trenches prior to filling the backside trenches with a material.

7. The method of claim 1 wherein filling the backside trenches with a material comprises filling the backside trenches with one of oxide and polysilicon.

8. The method of claim 1 wherein forming at least one antireflective layer over the filled backside trenches on the backside surface of the sensor layer further comprises:

forming an antireflective oxide layer on the backside surface of the sensor layer; and

forming an antireflective nitride layer over the antireflective oxide layer.

9. The method of claim 1 further comprising implanting a dopant into the sensor layer to form backside passivation implant regions prior to forming at least one antireflective layer over the filled backside trenches.

10. The method of claim 1, further comprising implanting a dopant into the sensor layer to form backside passivation implant regions after forming at least one antireflective layer over the filled backside trenches.

11. The method of claim 8 wherein the antireflective oxide layer has a thickness of approximately 50 Angstroms and the antireflective nitride layer has a thickness of approximately 500 Angstroms.

12. The method of claim 1 further comprising:

depositing a photoresist over the at least one antireflective layer;

patterning the photoresist to form openings over the backside trenches; and

implanting a dopant through the openings to form backside well isolation implant regions corresponding to the backside trenches.

13. The method of claim 1 further comprising forming an oxide layer over said at least one antireflective layer prior to attaching the temporary carrier wafer, wherein the temporary carrier wafer is attached to a backside surface of the oxide layer.

14. The method of claim 1 wherein further processing the image sensor wafer to form the plurality of image sensors including the pixel arrays further comprises:

forming photosensitive elements of the pixel arrays in the frontside surface the sensor layer;

forming frontside trenches in the frontside surface of the sensor layer;

forming frontside field isolation implant regions corresponding to the frontside trenches;

filling the frontside trenches with a material;

forming frontside well isolation implant regions corresponding to the frontside trenches;

forming at least one dielectric layer on the frontside surface of the sensor layer; and

attaching a handle wafer to a frontside surface of said at least one dielectric layer.

15. The method of claim 14 further comprising:

removing the temporary carrier wafer after the handle wafer is attached to the frontside surface; and

separating the image sensor wafer into the plurality of image sensors.

16. The method of claim 14 wherein said at least one dielectric layer comprises an interlayer dielectric and further comprises an intermetal dielectric separating multiple levels of metallization.