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Method of fabricating semiconductor device

  • US 8,076,202 B2
  • Filed: 03/15/2010
  • Issued: 12/13/2011
  • Est. Priority Date: 08/28/1997
  • Status: Expired due to Fees
First Claim
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1. A manufacturing method of a semiconductor device including a trench gate MISFET, comprising:

  • step (a) preparing a semiconductor substrate having a semiconductor layer thereon, said semiconductor layer being formed by an epitaxial growth method, said semiconductor layer having a top surface, and said semiconductor substrate and semiconductor layer having a first conduction type;

    step (b) forming a trench on the top surface of the semiconductor layer;

    step (c) after step (b), forming a first insulating film over an inner surface of the trench including a side wall and an edge portion of the trench by a thermal oxidation method, said edge portion being a portion of intersection of the inner surface of the trench and a major surface of the semiconductor substrate;

    step (d) after step (c), forming a second insulating film on the first insulating film by a deposition method, said first and second insulating films being formed so as to cover the edge portion of the trench, and said first and second insulating films acting as a gate insulating film of the MISFET;

    step (e) after step (d), forming a gate electrode of the MISFET on the second insulating film in the trench;

    step (f) after step (e), introducing first impurities to form a channel forming region of the MISFET in the semiconductor layer, said channel forming region having a second conduction type opposite to the first conduction type, said channel forming region being adjacent to the trench, a bottom surface of the trench being positioned below a bottom surface of the channel forming region, and said first and second insulating films being placed between the gate electrode and channel forming region; and

    step (g) after step (e), introducing second impurities to form a source region of the MISFET on the channel forming region in the semiconductor layer, said source region having the first conduction type, said source region being adjacent to the trench, said first and second insulating films being placed between the gate electrode and source region, andwherein, after said step (d), a thickness of said second insulating film formed over said sidewall of said trench is greater than a thickness of said first insulating film formed over said sidewall of said trench, andwherein said second insulating film includes nitrogen.

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