Method of fabricating semiconductor device

• US 8,076,202 B2
• Filed: 03/15/2010
• Issued: 12/13/2011
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Numazawa, Sumito, Nakazawa, Yoshito, Kobayashi, Masayoshi, Kudo, Satoshi, Imai, Yasuo, Kubo, Sakae, Shigematsu, Takashi, Ohnishi, Akihiro, Uesawa, Kozo, Oishi, Kentaro
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Scarlett, Shaka
• Application Number:
  US12/724,323
• Publication Number:
  US 20100173461A1
• Time in Patent Office: 638 Days
• Field of Search: 257/E21.428, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A manufacturing method of a semiconductor device including a trench gate MISFET, comprising:

step (a) preparing a semiconductor substrate having a semiconductor layer thereon, said semiconductor layer being formed by an epitaxial growth method, said semiconductor layer having a top surface, and said semiconductor substrate and semiconductor layer having a first conduction type;

step (b) forming a trench on the top surface of the semiconductor layer;

step (c) after step (b), forming a first insulating film over an inner surface of the trench including a side wall and an edge portion of the trench by a thermal oxidation method, said edge portion being a portion of intersection of the inner surface of the trench and a major surface of the semiconductor substrate;

step (d) after step (c), forming a second insulating film on the first insulating film by a deposition method, said first and second insulating films being formed so as to cover the edge portion of the trench, and said first and second insulating films acting as a gate insulating film of the MISFET;

step (e) after step (d), forming a gate electrode of the MISFET on the second insulating film in the trench;

step (f) after step (e), introducing first impurities to form a channel forming region of the MISFET in the semiconductor layer, said channel forming region having a second conduction type opposite to the first conduction type, said channel forming region being adjacent to the trench, a bottom surface of the trench being positioned below a bottom surface of the channel forming region, and said first and second insulating films being placed between the gate electrode and channel forming region; and

step (g) after step (e), introducing second impurities to form a source region of the MISFET on the channel forming region in the semiconductor layer, said source region having the first conduction type, said source region being adjacent to the trench, said first and second insulating films being placed between the gate electrode and source region, and

wherein, after said step (d), a thickness of said second insulating film formed over said sidewall of said trench is greater than a thickness of said first insulating film formed over said sidewall of said trench, and

wherein said second insulating film includes nitrogen.

2. A manufacturing method according to claim 1,

wherein said semiconductor substrate has a bottom surface;

and

said semiconductor substrate and semiconductor layer are placed between the top surface and bottom surface.

3. A manufacturing method according to claim 2,

further comprising:

step (h) forming a drain electrode of the MISFET on the bottom surface of the semiconductor substrate, said drain electrode being electrically connected with the semiconductor substrate and semiconductor layer.

9. A manufacturing method according to claim 1,

further comprising:

step (i), between said steps (b) and (c), performing a dry etching to said trench such that said edge portion of said trench becomes smooth.

13. A manufacturing method according to claim 1,

further comprising:

step (j), after said step (b), forming a third insulating film on said inner surface of the trench by a thermal oxidation method, and

step (k), between steps (j) and (c), removing said third insulating film.

4. A manufacturing method of a semiconductor device including a trench gate MISFET, comprising:

step (a) preparing a semiconductor substrate having a semiconductor layer thereon, said semiconductor layer having a top surface, said semiconductor substrate having a bottom surface, and said semiconductor substrate and semiconductor layer having a first conduction type;

step (b) forming a trench on the top surface of the semiconductor layer;

step (c) after step (b), forming a first insulating film over an inner surface of the trench including a side wall and an edge portion of the trench by a thermal oxidation method, said edge portion being a portion of intersection of the inner surface of the trench and a major surface of the semiconductor substrate;

step (d) after step (c), forming a second insulating film on the first insulating film by a deposition method, said first and second insulating films being formed so as to cover the edge portion of the trench, and said first and second insulating film acting as a gate insulating film of the MISFET;

step (e) after step (d), forming a gate electrode of the MISFET on the second insulating film in the trench;

step (f) after step (e), forming a channel forming region of the MISFET in the semiconductor layer having the first conduction type, said channel forming region having a second conduction type opposite to the first conduction type; and

step (g) after step (e), forming a source region of the MISFET on the channel forming region in the semiconductor layer, said source region having the first conduction type,

wherein, after said step (d), a thickness of said second insulating film formed over said sidewall of said trench is greater than a thickness of said first insulating film formed over said sidewall of said trench, and

wherein said second insulating film includes nitrogen.

10. A manufacturing method according to claim 4,

further comprising:

step (i), between said steps (b) and (c), performing a dry etching to said trench such that said edge portion of said trench becomes smooth.

14. A manufacturing method according to claim 4,

further comprising:

step (j), after said step (b), forming a third insulating film on said inner surface of the trench by a thermal oxidation method, and

step (k), between steps (j) and (c), removing said third insulating film.

5. A manufacturing method of a semiconductor device including a trench gate MISFET, comprising:

step (a) preparing a semiconductor substrate having a semiconductor layer thereon, said semiconductor layer having a top surface, said semiconductor substrate having a bottom surface, and said semiconductor substrate and semiconductor layer having a first conduction type;

step (b) forming a trench on the top surface of the semiconductor layer;

step (c) after step (b), forming a first insulating film over an inner surface of the trench including a side wall and an edge portion of the trench;

step (d) after step (c), forming a second insulating film on the first insulating film in the trench, said first and second insulating films being formed so as to cover the edge portion of the trench;

step (e) after step (d), forming a gate electrode of the MISFET on the second insulating film in the trench;

step (f) after step (e), forming a channel forming region of the MISFET in the semiconductor layer, said channel forming region having a second conduction type opposite to the first conduction type; and

step (g) after step (e), forming a source region of the MISFET on the channel forming region in the semiconductor layer, said source region having the first conduction type,

wherein, after said step (d), a thickness of said second insulating film formed over said sidewall of said trench is greater than a thickness of said first insulating film formed over said sidewall of said trench, and

wherein said second insulating film includes nitrogen.

11. A manufacturing method according to claim 5,

further comprising:

step (i), between said steps (b) and (c), performing a dry etching to said trench such that said edge portion of said trench becomes smooth.

15. A manufacturing method according to claim 5,

further comprising:

step (j), after said step (b), forming a third insulating film on said inner surface of the trench by a thermal oxidation method, and

step (k), between steps (j) and (c), removing said third insulating film.

6. A manufacturing method of a semiconductor device including a trench gate MISFET, comprising:

step (a) preparing a semiconductor substrate having a top surface and a bottom surface opposite to the top surface, said semiconductor substrate having a first conduction type;

step (b) forming a trench on the top surface of the semiconductor layer;

step (c) after step (b), forming a first insulating film on an inner surface of the trench including a side wall;

step (d) after step (c), forming a second insulating film on the first insulating film in the trench, said first and second insulating films being formed so as to cover an edge portion of the trench;

step (e) after step (d), forming a gate electrode of the MISFET on the second insulating film in the trench;

step (f) after step (e), forming a channel forming region of the MISFET over the semiconductor substrate, said channel forming region having a second conduction type opposite to the first conduction type; and

step (g) after step (e), forming a source region of the MISFET over the semiconductor substrate, said source region having the first conduction type,

wherein, after said step (d), a thickness of said second insulating film formed over said sidewall of said trench is greater than a thickness of said first insulating film formed over said sidewall of said trench, and

wherein said second insulating film includes nitrogen.

7. A manufacturing method according to claim 6,

wherein said first and second insulating films act as a gate insulating film of the MISFET.

8. A manufacturing method according to claim 6,

further comprising:

step (h) forming a drain electrode of the MISFET on the bottom surface of the semiconductor substrate, said drain electrode being electrically connected with the semiconductor substrate.

12. A manufacturing method according to claim 6,

further comprising:

step (i), between said steps (b) and (c), performing a dry etching to said trench such that said edge portion of said trench becomes smooth.

16. A manufacturing method according to claim 6,

further comprising:

step (j), after said step (b), forming a third insulating film on said inner surface of the trench by a thermal oxidation method, and

step (k), between steps (j) and (c), removing said third insulating film.