Methods for fabricating MOS devices having highly stressed channels

• US 8,076,209 B2
• Filed: 04/30/2010
• Issued: 12/13/2011
• Est. Priority Date: 09/29/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: YANG, Frank Bin, Pal, Rohit, Hargrove, Michael J.
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US12/771,948
• Publication Number:
  US 20100210084A1
• Time in Patent Office: 592 Days
• Field of Search: 438/269, 438/299, 438/369, 438/595, 257/288, 257/369, 257/E27.108, 257/E21.632
• US Class Current: 438/299
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Claims

1. A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising:

depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;

amorphizing the polysilicon layer;

forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;

forming offset spacers adjacent the sidewalls of the gate electrode;

etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the recesses exposing second surfaces of the silicon-comprising substrate;

depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the second surfaces;

annealing the silicon-comprising substrate;

removing the stress-inducing silicon nitride layer; and

after removing the stress-inducing silicon nitride layer, epitaxially forming impurity-doped, silicon-comprising regions in the recesses.

2. The method of claim 1, wherein depositing the stress-inducing silicon nitride layer comprises depositing a stress-inducing silicon nitride layer having a thickness in a range of from about 30 nm to about 70 nm.

3. The method of claim 1, wherein depositing the stress-inducing silicon nitride layer comprises depositing a tensile stress-inducing silicon nitride layer.

4. The method of claim 1, wherein depositing the stress-inducing silicon nitride layer comprises depositing a compressive stress-inducing silicon nitride layer.

5. The method of claim 1, wherein etching the first surface comprises etching the first surface to form recesses having a depth in a range of from about 50 nm to about 100 nm.

6. The method of claim 1, wherein epitaxially forming impurity-doped, silicon-comprising regions comprises epitaxially forming impurity-doped, silicon-comprising regions further comprising carbon or germanium.

7. A method for forming a semiconductor device comprising a silicon-comprising substrate, wherein the method comprises:

depositing a polysilicon layer overlying the silicon-comprising substrate;

amorphizing the polysilicon layer;

etching the amorphized polysilicon layer to form a gate electrode;

etching recesses into the substrate using the gate electrode as an etch mask;

depositing a stress-inducing layer overlying the gate electrode after etching recesses into the substrate;

annealing the silicon-comprising substrate;

removing the stress-inducing layer; and

after removing the stress-inducing layer, epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

8. The method of claim 7, wherein depositing the stress-inducing layer comprises depositing a compressive stress-inducing layer in the recesses.

9. The method of claim 8, wherein annealing the silicon-comprising substrate results in a longitudinal compressive stress in a channel region underlying the gate electrode, the longitudinal compressive stress being generated by the compressive stress-inducing layer deposited in the recesses.

10. The method of claim 7, wherein depositing the stress-inducing layer comprises depositing a tensile stress-inducing layer in the recesses.

11. The method of claim 10, wherein annealing the silicon-comprising substrate results in a longitudinal tensile stress in a channel region underlying the gate electrode, the longitudinal tensile stress being generated by the tensile stress-inducing layer deposited in the recesses.

12. The method of claim 7, the stress-inducing layer being deposited in the recesses, wherein epitaxially growing impurity-doped, silicon-comprising regions in the recesses supplements stress induced in a channel region underlying the gate electrode by the stress-inducing layer deposited in the recesses.

13. The method of claim 7, wherein annealing the silicon-comprising substrate results in a stress substantially orthogonal to a surface of the silicon-comprising substrate being transferred to a channel region underlying the gate electrode.

14. The method of claim 7, wherein annealing the silicon-comprising substrate is performed after depositing the stress-inducing layer and prior removing the stress-inducing layer.

15. The method of claim 7, wherein etching recesses comprises etching recesses having a depth in a range of from about 50 nm to about 100 nm.

16. A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising:

depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;

amorphizing the polysilicon layer;

forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;

forming offset spacers adjacent the sidewalls of the gate electrode;

etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate;

depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the recesses;

annealing the silicon-comprising substrate;

removing the stress-inducing silicon nitride layer; and

after removing the stress-inducing silicon nitride layer, epitaxially forming impurity-doped, silicon-comprising regions in the recesses.

17. The method of claim 16, wherein annealing the silicon-comprising substrate results in a longitudinal stress being transferred from the gate stack to a channel region of the silicon-comprising substrate underlying the gate stack, wherein a longitudinal stress generated by the stress-inducing silicon nitride layer deposited in the recesses supplements the longitudinal stress transferred from the gate stack.

18. The method of claim 16, wherein epitaxially growing impurity-doped, silicon-comprising regions in the recesses supplements stress induced in a channel region underlying the gate stack by the stress-inducing silicon nitride layer deposited in the recesses.

19. The method of claim 16, wherein etching recesses comprises anisotropically etching recess into the silicon-comprising substrate proximate the gate stack.

20. The method of claim 16, wherein annealing the silicon-comprising substrate is performed after depositing the stress-inducing silicon nitride layer and prior to removing the stress-inducing silicon nitride layer.