Power module assembly with reduced inductance

• US 8,076,696 B2
• Filed: 10/30/2009
• Issued: 12/13/2011
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Beaupre, Richard Alfred, Delgado, Eladio Clemente, Stevanovic, Ljubisa Dragoljub
• Primary Examiner(s): Ha, Nathan
• Application Number:
  US12/609,400
• Publication Number:
  US 20110101515A1
• Time in Patent Office: 774 Days
• Field of Search: 257/177, 257/178, 257/691, 257/693, 257/E23.169
• US Class Current: 257/177
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.

Claims

1. A device comprising:

a first conductive substrate;

a second conductive substrate;

a first power semiconductor component that has a first thickness and is electrically coupled to said first conductive substrate;

a second power semiconductor component that has a second thickness and is electrically coupled to said second conductive substrate;

a positive terminal electrically coupled to said first conductive substrate;

a negative terminal electrically coupled to said second power semiconductor component via a conductor that extends generally along a connection direction; and

an output terminal electrically coupled to said first power semiconductor component and said second conductive substrate,

wherein said positive and negative terminals, said first and second power semiconductor components, and said first and second conductive substrates are incorporated into a common circuit loop and are configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness, and

wherein said first and second power semiconductor components are respectively disposed on opposing sides of said positive terminal and of said negative terminal, and said first and second power semiconductor components are generally disposed so as to be aligned along the connection direction.

2. The device of claim 1, further comprising a respective diode connected in an anti-parallel arrangement across each of said first and second power semiconductor components.

3. The device of claim 1, wherein said positive and negative terminals, said first and second power semiconductor components, and said first and second conductive substrates are configured such that a first width of the circuit loop in at least one direction is about equal to the first thickness and a second width of the circuit loop in at least one direction is about equal to the second thickness, and the circuit loop everywhere has a width that is less than or about equal to the greater of the first thickness and the second thickness.

4. The device of claim 1, wherein said positive and negative terminals, said first and second power semiconductor components, and said first and second conductive substrates are configured such that a first width of the circuit loop in at least one direction is defined by the first thickness and a second width of the circuit loop in at least one direction is defined by the second thickness.

5. The device of claim 1, wherein said positive, negative, and output terminals are configured to support an instantaneous electrical current of at least about 10 A.

6. The device of claim 1, wherein said negative terminal substantially opposes said positive terminal.

7. The device of claim 1, wherein said positive and negative terminals abut opposing sides of a power insulation layer.

8. The device of claim 1, wherein said first and second power semiconductor components respectively include at least one component selected from the group consisting of an insulated gate bipolar transistor, a metal-oxide-semiconductor field effect transistor, a diode, and a thyristor.

9. The device of claim 1, wherein said first and second power semiconductor components respectively include a component formed of silicon carbide.

10. The device of claim 1, further comprising a substantially planar baseplate, and wherein said first and second conductive substrates are respectively disposed on said baseplate and said positive and negative terminals extend substantially perpendicularly away from said baseplate.

11. The device of claim 1, further comprising an output insulation layer, and wherein said output terminal and said positive terminal abut opposing sides of said output insulation layer, and said output terminal and said negative terminal abut opposing sides of said output insulation layer.

12. The device of claim 1, wherein said first and second power semiconductor components are respectively disposed on said first and second conductive substrates.

13. The device of claim 1, wherein each of said first and second power semiconductor components include opposing front and back surfaces, said back surface of said first power semiconductor component being electrically coupled to said first conductive substrate and said back surface of said second power semiconductor component being electrically coupled to said second conductive substrate.

14. The device of claim 1, wherein said positive and negative terminals are substantially planar.

15. The device of claim 1, further comprising a connector configured to electrically couple said positive and negative terminals to respective busbars.

16. The device of claim 15, wherein said positive and negative terminals abut opposing sides of a power insulation layer, and wherein said connector includes opposing electrodes configured to make respective electrical contact with said positive terminal and said negative terminal, and wherein a separation distance between said opposing electrodes is substantially similar to an aggregate thickness of said positive and negative terminals and said power insulation layer.

17. The device of claim 1, further including positive leads, negative leads, first output leads, and second output leads, and wherein said positive leads electrically couple said positive terminal and said first conductive substrate, said negative leads electrically couple said negative terminal and said second power semiconductor component, said first output leads electrically couple said output terminal and said first power semiconductor component, and said second output leads electrically couple said output terminal and said second conductive substrate.

18. The device of claim 17, wherein each of said positive leads is proximal to a respective first output lead substantially along a length of said respective positive lead, and each of said second output leads is proximal to a respective negative lead substantially along a length of said respective second output lead.

19. The device of claim 17, wherein each of said leads includes a wire bond.