Semiconductor device with trench of various widths

• US 8,076,735 B2
• Filed: 10/02/2009
• Issued: 12/13/2011
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hsien
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/572,498
• Publication Number:
  US 20110079854A1
• Time in Patent Office: 802 Days
• Field of Search: 257/310, 257/407, 257/E29.15, 257/E29.16
• US Class Current: 257/407
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.

Claims

1. A semiconductor device, comprising:

a substrate, disposed with a dielectric layer thereon, wherein a trench is disposed in the dielectric layer;

a gate structure, located in the trench and comprising a high dielectric constant layer, a work function metal layer, and a metal layer sequentially disposed on the substrate; and

a source/drain region, disposed in the substrate at respective sides of the gate structure,

wherein the trench comprises a top, a bottom, and a neck arranged between the top and the bottom, a width of the neck is narrower than a width of the top, and the width of the neck is narrower than or equal to a width of the bottom.

2. The semiconductor device as claimed in claim 1, wherein the top and the neck have a first height therebetween, the neck and the bottom have a second height therebetween, and a ratio of the first height to the second height is substantially 2:

1.

3. The semiconductor device as claimed in claim 1, wherein an included angle between a sidewall of the top of each of the plurality of trenches and a surface of the dielectric layer is larger than 90°

.

4. The semiconductor device as claimed in claim 1, further comprising an insulation layer disposed between the substrate and the high dielectric constant layer.

5. The semiconductor device as claimed in claim 1, wherein the source/drain region is a doped region or an epitaxial layer.

6. The semiconductor device as claimed in claim 1, further comprising a spacer disposed on a sidewall of the gate structure.