Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

• US 8,076,756 B2
• Filed: 02/19/2011
• Issued: 12/13/2011
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lane, Michael W., Liu, Xiao Hu, Shaw, Thomas M., Farooq, Mukta G., Hannon, Robert, Melville, Ian D. W.
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/031,195
• Publication Number:
  US 20110140245A1
• Time in Patent Office: 297 Days
• Field of Search: 257/620, 438/33, 438/465
• US Class Current: 257/620
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/18301 being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Claims

1. A semiconductor product comprising:

a semiconductor substrate having a top surface and a bottom surface;

a semiconductor chip with an active device layer, and with an interconnection layer formed above both said active device layer and said substrate;

said semiconductor product having an upper surface and a perimeter;

a crack stop barrier formed in said chip within said perimeter; and

a trench cut extending down through said interconnection layer and said upper surface of said semiconductor product, but extending only partially down into said active device layer or only partially through said top surface into said substrate between said perimeter and said crack stop barrier.

2. The semiconductor product of claim 1 comprising:

a semiconductor device formed in said active device layer of said product; and

said interconnection layer containing dielectric layers, interconnect lines and vias.

3. The semiconductor product of claim 2 wherein an underfill layer is formed over said product covering said interconnection layer and filling said trench.

4. The semiconductor product of claim 2 wherein said interconnection structure includes a low-k dielectric material.

5. The semiconductor product of claim 2 wherein:

said barrier extends through said interconnection layer at least into contact with said semiconductor substrate; and

said trench extends at least partially through said semiconductor layer.

6. The semiconductor product of claim 5 wherein an underfill layer is formed over said product covering said interconnection structure and filling said trench.

7. The semiconductor product of claim 6 wherein said low-k dielectric material comprises porous hydrogenated silicon oxycarbide (pSiCOH.).

8. The semiconductor product of claim 2 wherein said interconnection structure is recessed down to said substrate outboard from said trench.

9. The semiconductor product of claim 8 wherein said trench has a bottom which is flared outwardly.

10. The semiconductor product of claim 1 wherein:

said trench is spaced laterally with respect to said top surface of said substrate; and

said trench extends through and into said top surface of said substrate and is spaced from said diced edge of said chip.

11. The semiconductor product of claim 1 wherein a plurality of trenches are formed nested one inside another in a sequence of trenches of increasing lateral dimensions are formed cut into said top surface of said semiconductor chip surrounding said barrier, between said perimeter and said barrier.

12. The semiconductor product of claim 11 wherein said interconnection structure is recessed down to said substrate outboard from said trench.

13. The semiconductor product of claim 1 wherein said trench is slanted at an angle with respect to said top surface.

14. The semiconductor product of claim 1 comprising:

said interconnection layer containing dielectric layers, interconnect lines and vias;

said interconnection structure including a low-k dielectric material; and

said low-k dielectric material comprising porous hydrogenated silicon oxycarbide (pSiCOH.).

15. A semiconductor product comprising:

a semiconductor substrate having a top surface and a bottom surface

a semiconductor chip formed including said substrate,

said semiconductor chip having a Front End Of Line (FEOL) layer with an upper surface formed above said top surface and having a Back End Of Line (BEOL) layer including therein an interconnection structure formed above said upper surface;

said semiconductor chip and said interconnection structure having a perimeter;

a barrier edge selected from the group consisting of a crackstop barrier and a perimeter with a diced edge on said perimeter; and

a trench cut into said semiconductor chip between said diced edge and said barrier edge.

16. The semiconductor product of claim 15 comprising:

a semiconductor device formed in said chip; and

said interconnection layer containing dielectric layers, interconnect lines and vias.

17. The semiconductor product of claim 16 wherein:

an underfill layer is formed over said product covering said interconnection structure and filling said trench;

said interconnection structure includes a low-k dielectric material.

18. The semiconductor product of claim 17 wherein:

said barrier extends through said interconnection structure at least into contact with said semiconductor substrate; and

said trench extends at least partially through said semiconductor layer.

19. The semiconductor product of claim 16 wherein an underfill layer is formed over said product covering said interconnection structure and filling said trench.

20. A semiconductor product comprising:

said semiconductor product having a top surface and a bottom surface including a semiconductor chip;

said semiconductor product having an upper surface and a perimeter, with a crack stop barrier formed in said chip within said perimeter, and with an active device Front End Of Line (FEOL) layer and a Back End Of Line (BEOL) layer above said FEOL layer with said BEOL layer including an interconnection structure with said FEOL and BEOL layers formed above said top surface of said substrate;

a barrier formed in said chip within said perimeter;

a trench cut extending down through said upper surface of said semiconductor product between said perimeter and said barrier but extending only partially down into said active device FEOL layer or said substrate between said crack stop barrier and the outermost of said perimeter; and

a blanket underfill layer over said product completely covering said interconnection structure and completely filling said trench.