Thin film transistor substrate and method of manufacturing the same

• US 8,077,268 B2
• Filed: 06/17/2008
• Issued: 12/13/2011
• Est. Priority Date: 07/27/2007
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Eun-Guk, Jeong, Chang-Oh, Lee, Je-Hun, Kim, Do-Hyun, Lim, Soon-Kwon
• Primary Examiner(s): Vu, Phu
• Application Number:
  US12/140,655
• Publication Number:
  US 20090026450A1
• Time in Patent Office: 1,274 Days
• Field of Search: 349/43
• US Class Current: 349/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

Claims

1. A thin film transistor array substrate comprising:

a base substrate;

a first wire on the base substrate;

a first insulating layer on the base substrate to cover the first wire;

a semiconductor layer on the first insulating layer;

a second insulating layer on the first insulating layer on which the semiconductor layer is formed, the second insulating layer having a contact hole extending to the semiconductor layer;

a second wire on the second insulating layer, a portion of the second wire making contact with the semiconductor layer through the contact hole, the second wire including a first conductive layer and a second conductive layer formed on the first conductive layer; and

a pixel electrode including a same layer as the first conductive layer, the pixel electrode making contact with a portion of the second wire.

2. The thin film transistor array substrate of claim 1, wherein the semiconductor layer comprises semiconductor oxide.

3. The thin film transistor array substrate of claim 2, wherein the semiconductor oxide comprises zinc oxide.

4. The thin film transistor array substrate of claim 3, wherein the semiconductor oxide comprises at least one selected from the group consisting of indium and gallium.

5. The thin film transistor array substrate of claim 1, wherein the second conductive layer includes a different material from the first conductive layer.

6. The thin film transistor array substrate of claim 5, wherein the first conductive layer includes conductive oxide.

7. The thin film transistor array substrate of claim 6, wherein the conductive oxide includes indium tin oxide (ITO) or indium zinc oxide (IZO).

8. The thin film transistor array substrate of claim 5, wherein the first conductive layer includes a gate line and a gate electrode electrically connected to the gate line,

the second conductive layer includes a data line, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, and

the source electrode and the drain electrode are electrically connected to the semiconductor layer through contact holes formed through the second insulating layer, respectively.

9. The thin film transistor array substrate of claim 8, wherein the first conductive layer includes a first gate pad electrode electrically connected to the gate line.

10. The thin film transistor array substrate of claim 9, wherein the first conductive layer includes a second gape pad electrode electrically connected to the first gate pad electrode through a contact hole formed through the first insulating layer.

11. The thin film transistor array substrate of claim 10, wherein the second conductive layer includes a third gate pad electrode on the second gate pad electrode.

12. The thin film transistor array substrate of claim 8, wherein the first conductive layer includes a first data pad electrode electrically connected to the data line.

13. The thin film transistor array substrate of claim 12, wherein the second conductive layer includes a second data pad electrode on the first data pad electrode.

14. The thin film transistor array substrate of claim 8, wherein the first conductive layer includes a pixel electrode electrically connected to the drain electrode.

15. A manufacturing method of a thin film transistor array substrate comprising:

forming a first wire on a base substrate;

forming a first insulating layer on the base substrate to cover the first wire;

forming a semiconductor layer on the first insulating layer;

forming a second insulating layer on the first insulating layer on which the semiconductor layer is formed;

forming a contact hole in the second insulating layer;

forming a first conductive layer on the second insulating layer;

forming a second conductive layer on the first conductive layer;

forming a second wire and a pixel electrode on the second insulating layer by patterning the first and second conductive layers so that a portion of the second wire makes contact with the semiconductor layer through the contact hole, and the pixel electrode includes the first conductive layer and makes contact with a portion of the second wire.

16. The manufacturing method of claim 15,

wherein the second conductive layer includes a different material from the first conductive layer, and

wherein forming the second wire and the pixel electrode comprises etching the first and second conductive layers to form a first conductive pattern and a second conductive pattern, respectively.

17. The manufacturing method of claim 16, wherein forming the first and second conductive patterns includes:

first etching the first and second conductive layers to form the first conductive pattern from the first conductive layer; and

second etching the first etched second conductive layer to form the second conductive pattern from the second conductive layer.

18. The manufacturing method of claim 17, wherein a first gate pad electrode and a first data pad electrode are formed from the first conductive layer through the first etching, and a second gate pad electrode and a second data pad electrode are formed from the second conductive layer through the first etching.

19. The manufacturing method of claim 18, wherein the gate pad electrode and the second data pad electrode are removed through the second etching.

20. The manufacturing method of claim 15, wherein the semiconductor layer includes semiconductor oxide.