Nonvolatile memory device and method of driving the same

• US 8,077,496 B2
• Filed: 09/23/2009
• Issued: 12/13/2011
• Est. Priority Date: 09/26/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Byung-Gil
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Tran, Anthan
• Application Number:
  US12/585,730
• Publication Number:
  US 20100080040A1
• Time in Patent Office: 811 Days
• Field of Search: 365/148, 365/158
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes

Abstract

A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance memory cells and the bit lines to receive a first control voltage being applied to their gates, includes making the first control voltage at a first level, and changing a resistance of the variable resistance memory cells by providing a write bias to the variable resistance cells; verifying and reading whether the changed resistance enters into a specified resistance window; and changing the first control voltage to a second level that is different from the first level, and changing the resistance of the variable resistance memory cells by providing the write bias to the variable resistance memory cells.

Claims

1. A method of driving a nonvolatile memory device including a plurality of variable resistance memory cells, each of the plurality of variable resistance memory cells having a bit line coupled to the variable resistance memory cell and a column selection transistor coupled between the variable resistance memory cell and the bit line to receive a first control voltage being applied to a gate of the column selection transistor, the method comprising:

setting the first control voltage at a first level;

changing a resistance of a selected memory cell from among the plurality of variable resistance memory cells by providing a write bias to the selected memory cell while setting the first control voltage;

determining whether the changed resistance of the selected memory cell enters into a desired resistance window;

changing, based on the determining step, the first control voltage to a second level that is different from the first level; and

changing the resistance of the selected memory cells by providing the write bias to the selected memory cell while changing the first control voltage.

2. The method of claim 1, wherein the changing the first control voltage and the changing the resistance of the selected memory cell in accordance with the determining are repeated until the changed resistance enters into the desired resistance window .

3. The method of claim 2, wherein the second level is a level higher than the first level, and the changing the first control voltage is repeated so as to increase the voltage level of the first control voltage in stages from a low level to the high level.

4. The method of claim 3, wherein the write bias is provided during a write loop, and the write loop is repeated at least once until the changed resistances of the plurality of variable resistance memory cells enter into the desired resistance window.

5. The method of claim 4, wherein the stages of the voltage levels of the first control voltage increase with each repeating of the write loop.

6. The method of claim 1, wherein the plurality of variable resistance memory cells are two-bit cells.

7. The method of claim 1, wherein the bit line is a local bit line, and the column selection transistor is a local column selection transistor;

the nonvolatile memory device further comprises a global bit line coupled to the local bit line, and a global column selection switching element selectively connecting the local bit line and the global bit line; and

the changing the resistance of the selected memory cell in accordance with the determining further comprises changing a voltage level of a second control voltage being applied to the global column selection switching element.

8. A method of driving a nonvolatile memory device including a plurality of variable resistance memory cells, each of the plurality of variable resistance memory cells having a bit line coupled to the variable resistance memory cell and column selection transistor coupled between the variable resistance memory cell and the bit lines to receive a first control voltage being applied to a gate of the column selection transistor, the method comprising:

during a first write verify operation, writing write data by providing a write bias to a selected memory cell from among the plurality variable resistance memory cells; and

during a second write verify operation, writing the write data by providing the write bias to the selected variable resistance memory cell,

wherein a level of the first control voltage in the first write verify operation is different from a level of the first control voltage in the second write verify operation.

9. The method of claim 8, wherein the second write verify operation is performed several times until a resistance of the selected memory cell enters into a desired resistance window.

10. The method of claim 8, wherein the level of the first control voltage in the second write verify operation is higher than the level of the first control voltage in the first write verify operation.

11. The method of claim 8, wherein the plurality of variable resistance memory cells are two-bit cells.

12. The method of claim 8, wherein the bit line is a local bit line, and the column selection transistor is a local column selection transistor;

the nonvolatile memory device further comprises a global bit line coupled to the local bit line, and global column selection switching element selectively connecting the local bit line and the global bit line, a second control voltage being applied to the global column selection switching element; and

a level of the second control voltage in the first write verify operation is different from a level of the second control voltage in the second write verify operation.

13. A nonvolatile memory device comprising:

a plurality of variable resistance memory cells;

bit lines coupled to the plurality of variable resistance memory cells, respectively;

column selection transistors coupled between the plurality of variable resistance memory cells and the bit lines, respectively, each of the column selection transistors being configured to receive a first control voltage being applied to a gate of the column selection transistor; and

a write circuit coupled to the bit lines configured perform a write operation by providing a write bias to a selected memory cell from among the plurality of variable resistance memory cells to write data, the write circuit being configured to perform the write operation through one or more successive write verify operations,

wherein a level of the first control voltage in a previous write verify operation is different from a level of the first control voltage in a subsequent write verify operation.

14. The nonvolatile memory device of claim 13, wherein the write verify operation is performed several times until a resistance of the selected memory cell enters into a desired resistance window.

15. The nonvolatile memory device of claim 14, further comprising:

a verify sense amplifier configured to determine whether the resistance of the selected memory cell enters into the desired resistance window; and

a control unit configured to provide a control signal for changing the level of the first control voltage in accordance with the result of verification.

16. The nonvolatile memory device of claim 13, wherein the level of the first control voltage in the subsequent write verify operation is higher than the level of the first control voltage in the previous write verify operation.

17. The nonvolatile memory device of claim 13, wherein the column selection transistor is an nMOS transistor, and a resistance level of the selected memory cell increases substantially in proportion to increases in the voltage level of the first control voltage.

18. The nonvolatile memory device of claim 13, wherein the plurality of variable resistance memory cells are two-bit cells.

19. The nonvolatile memory device of claim 13, wherein each of the plurality of variable resistance memory cells is one of a phase change random access memory (PRAM) cell and a resistive RAM (RRAM) cell.

20. The nonvolatile memory device of claim 13, wherein the bit lines are local bit lines, and the column selection transistors are local column selection transistors;

the nonvolatile memory device further comprises global bit lines coupled to the local bit lines, and global column selection switching elements configured to selectively connectithe local bit lines and the global bit lines, a second control voltage being applied to the global column selection switching elements; and

a level of the second control voltage in the previous write verify operation is different from a level of the second control voltage in the subsequent write verify operation.