Hybrid non-volatile memory

• US 8,077,511 B2
• Filed: 07/27/2007
• Issued: 12/13/2011
• Est. Priority Date: 04/21/2004
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Pesavento, Alberto
• Primary Examiner(s): Nguyen, Dang T
• Application Number:
  US11/829,370
• Publication Number:
  US 20080205150A1
• Time in Patent Office: 1,600 Days
• Field of Search: 365/185.01, 365/185.28, 365/96, 365/185.33, 711/103, 711/170
• US Class Current: 365/185.01
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability

Abstract

A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.

Claims

1. A hybrid Non-Volatile Memory (NVM) device, comprising:

a first circuit of a first type NVM cell for storing data for a first operational component;

a second circuit of a second type NVM cell that is different from the first type NVM cell, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component; and

support circuitry, wherein a portion of the support circuitry is arranged to support the first circuit and the second circuit,

wherein one of the first circuit and the second circuit is arranged to provide an output responsive to transitioning from a first power state to a second power state, and

wherein another of the first circuit and the second circuit is arranged to provide an output responsive to being addressed.

2. The NVM device of claim 1, wherein

the first circuit is arranged to provide an output faster than an output of the second circuit.

3. The NVM device of claim 1, wherein

one of the first circuit and the second circuit is arranged in an array configuration;

and wherein

another of the first circuit and the second circuit is arranged in a non-array configuration.

4. The NVM device of claim 1, further comprising:

at least one additional type NVM circuit, wherein the portion of the support circuitry is arranged to support also the at least one additional type NVM circuit.

5. The NVM device of claim 1, wherein

the first circuit is a programmable fuse circuit.

6. The NVM device of claim 5, wherein

the programmable fuse circuit includes at least one of:

a one time programmable (OTP) fuse cell and a multiple time programmable (MTP) fuse cell.

7. The NVM device of claim 5, wherein

the programmable fuse circuit is programmable for storing its logic value.

8. The NVM device of claim 5, wherein

the programmable fuse circuit is adapted to output its stored logic value responsive to receiving a Power On Reset (POR) signal.

9. The NVM device of claim 1, wherein

the second circuit is an ordinary NVM circuit that is arranged to provide a logic value to the second operational component.

26. The NVM device of claim 1, wherein

the first power state is a power-off state and the second power state is a power-on state.

10. A hybrid NVM device, comprising:

a first circuit for storing data for a first operational component, wherein the first circuit includes a plurality of NVM array bits arranged in rows and columns of an NVM array, and wherein a first portion of the NVM array bits are arranged to output their stored logic value faster than a second portion of the NVM array bits during a power-on state;

a second circuit that includes at least one NVM cell arranged to provide an output responsive to transitioning from a first power state to a second power state, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component;

support circuitry, wherein a portion of the support circuitry is shared by the first circuit and the second circuit; and

wherein the support circuitry include an addressing circuit that is arranged to cause the second portion of the NVM array bits to output their stored logic value in the power-on state.

11. The NVM device of claim 10, wherein

the first portion of the NVM array bits is arranged in the same manner as the second portion of the NVM array bits.

12. The NVM device of claim 10, wherein

the first portion of the NVM array bits includes at least one of a programmable bit and a fixed bit.

13. A hybrid NVM device, comprising:

a first circuit for storing data for a first operational component, wherein the first circuit includes a plurality of NVM array bits arranged in rows and columns of an NVM array, and wherein a first portion of the NVM array bits are arranged to output their stored logic value faster than a second portion of the NVM array bits during a power-on state;

a second circuit that includes at least one NVM cell arranged to provide an output responsive to transitioning from a first power state to a second power state, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component;

support circuitry, wherein a portion of the support circuitry is shared by the first circuit and the second circuit; and

wherein the support circuitry include an addressing circuit that is arranged to cause the second portion of the NVM array bits to output their stored logic value in the power-on state, wherein

the first portion of the NVM array bits includes at least one of a programmable bit and a fixed bit; and

the addressing circuit includes a by-passing circuit that is arranged to by-pass the fixed bit.

14. The NVM device of claim 13, wherein

the by-passing circuit includes at least one programmable bit.

15. A method for a hybrid NVM device, comprising:

storing a plurality of values in a plurality of NVM cells, wherein the NVM cells are adapted to store the values in a power-off state;

providing a first output from a first portion of NVM cells of a first type to a first operational component responsive to transitioning from a first power state to a second power state;

providing a second output from a second portion of NVM cells of a second type responsive to being addressed by support circuitry for a second operational component distinct from the first operational component, wherein a circuit for providing the second output is distinct from the first operational component and wherein the support circuitry is shared by the first portion of NVM cells and the second portion of NVM cells; and

providing a third output from a third portion of NVM cells for a third operational component;

wherein the third output is distinct from the second output.

16. The method of claim 15, wherein

the outputs of the third portion of NVM cells include one of an ON state and an OFF state for the third operational component.

17. The method of claim 15, wherein

the outputs of the second portion of NVM cells include logic values for the second operational component.

18. The method of claim 15, further comprising:

calibrating the first operational component using the output of the first portion of NVM cells;

calibrating the second operational component using the output of the second portion of NVM cells; and

calibrating the third operational component using the output of the third portion of NVM cells.

19. The method of claim 15, further comprising:

latching the output of the third portion of NVM cells; and

providing the latched outputs of the third portion of NVM cells to the third operational component.

20. The method of claim 15, further comprising:

outputting the second portion of NVM cells as a result of a stored value in at least one of the first portion of NVM cells.

21. The method of claim 15, wherein

the first portion of NVM cells includes at least one of:

a one time programmable (OTP) fuse cell and a multiple time programmable (MTP) fuse cell.

22. The method of claim 15, further comprising:

programming the first portion of NVM cells for storing their logic value.

23. The method of claim 22, further comprising:

evaluating a performance of at least one of the first, second, and third operational components; and

determining a value to be programmed in the first portion of NVM cells for improving the performance.

24. The method of claim 15, wherein

the second portion of the NVM cells are NVM bits of an NVM array, and the NVM bits are outputted as a result addressing of rows and columns of the NVM array by a control circuit.

25. The method of claim 24, wherein

the second portion of NVM bits includes at least one of a programmable bit and a fixed bit.

27. The NVM device of claim 15, wherein

the first power state is a power-off state and the second power state is a power-on state.