Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

• US 8,077,536 B2
• Filed: 07/31/2009
• Issued: 12/13/2011
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US12/533,661
• Publication Number:
  US 20100034041A1
• Time in Patent Office: 865 Days
• Field of Search: 365/222, 365/189.011, 365/174, 365/189.03
• US Class Current: 365/222
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.

Claims

1. A semiconductor memory array, including:

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell including;

a substrate having a top surface, said substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface;

a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; and

a gate positioned between said first and second regions and above said top surface;

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate;

a buried well terminal electrically connected to said buried layer; and

a substrate terminal electrically connected to said substrate below said buried layer;

wherein each said memory cell further includes a first data state which corresponds to a first charge in the body region, and a second data state which corresponds to a second charge in the body region;

wherein each of said terminals is controlled to perform operations on each said cell; and

wherein said terminals are controlled to perform a refresh operation by a non-algorithmic process.

2. The array of claim 1, wherein the data state of at least one of said cells is read by:

applying a neutral voltage state to said substrate terminal, applying a voltage greater than or equal to zero to said buried well terminal, applying a neutral voltage to said source line terminal, applying a positive voltage to said bit line terminal and applying a positive voltage to said word line terminal.

3. The array of claim 1, wherein the data state of at least one of said cells is read by:

applying a positive voltage to said substrate terminal, applying a neutral voltage to said bit line terminal, applying a positive voltage to said word line terminal and leaving said source line terminal and said buried well terminal floating.

4. The array of claim 1, wherein the first data state is written to at least one of said cells by:

applying a positive voltage to said bit line terminal, applying a neutral voltage to said source line terminal, applying a negative voltage to said word line terminal, applying a positive voltage to said buried well terminal and applying a neutral voltage to said substrate terminal.

5. The array of claim 1, wherein the first data state is written to at least one of said cells by:

applying a positive voltage to said substrate terminal, applying a neutral voltage to said source line terminal, applying a positive voltage to said bit line terminal, applying a positive voltage to said word line terminal and allowing said buried well terminal to float.

6. The array of claim 1, wherein the first data state is written to at least one of said cells by:

applying a neutral voltage to said bit line terminal, applying a positive voltage to said word line terminal, applying a positive voltage to said substrate terminal and allowing said source line terminal and said buried well terminal to float.

7. The array of claim 1, wherein the second data state is written to at least one of said cells by:

applying a negative voltage to said source line terminal, applying a voltage less than or equal to about zero to said word line terminal, applying a neutral voltage to said substrate terminal, applying a voltage greater than or equal to zero to said buried well terminal, and applying a neutral voltage to said bit line terminal.

8. The array of claim 1, wherein the second data state is written to at least one of said cells by:

applying a positive voltage to said bit line terminal, applying a positive voltage to said word line terminal, applying a positive voltage to said substrate terminal, while allowing said source line terminal and said buried well terminal to float.

9. The array of claim 1, wherein a holding operation is performed on at least one of said cells by:

applying a substantially neutral voltage to said bit line terminal, applying a neutral or negative voltage to said word line terminal, and applying a positive voltage to said substrate terminal, while allowing said source line terminal and said buried well terminal to float.

10. A semiconductor memory array, including:

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell including;

a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

a second region having said second conductivity type, said second region being spaced apart from said first region;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; and

a gate positioned between said first and second regions and adjacent said body region;

wherein each said memory cell further includes a first data state which corresponds to a first charge in the body region, and a second data state which corresponds to a second charge in the body region;

wherein said substrates of a plurality of said cells are connected to a same substrate terminal;

and wherein data states of said plurality of cells are maintained by biasing said substrate terminal.

11. The array of claim 10, wherein said cells are refreshed by a non-algorithmic process.

12. The array of claim 10, wherein said voltage applied to said substrate terminal automatically activates each cell of said plurality of cells that has said first data state to refresh said first data state, and wherein each cell of said plurality of cells that has said second data state automatically remains deactivated upon application of said voltage to said substrate terminal so that each said cell having said second data state remains in said second data state.

13. The array of claim 10, wherein said substrate terminal is periodically biased by pulsing said substrate terminal and wherein said data states of said plurality of cells are refreshed upon each said pulse.

14. The array of claim 10, wherein said substrate terminal is constantly biased and said plurality of cells constantly maintain said data states.

15. The array of claim 10, wherein said substrate has a top surface, said first region is formed in said substrate and exposed at said top surface;

wherein said second region is formed in said substrate and exposed at said top surface;

and wherein said gate is positioned above said top surface.

16. The array of claim 10, wherein said first and second regions are formed in a fin that extends above said buried layer, said gate is provided on opposite sides of said fin, between said first and second regions, and said body region is between said first and second regions and between said gate on opposite sides of said fin.

17. The array of claim 16, wherein said gate is additionally provided adjacent a top surface of said body region.

18. A method of maintaining the data state of a semiconductor dynamic random access memory cell, wherein said memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

a second region having said second conductivity type, said second region being spaced apart from said first region;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; and

a gate positioned between said first and second regions and adjacent said body region;

wherein said memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration, said method comprising;

providing said memory cell storing one of said first and second data states; and

applying a positive voltage to a substrate terminal connected to said substrate beneath said buried layer, wherein when said body region is in said first state, said body region turns on a silicon controlled rectifier device of said cell and current flows through said device to maintain configuration of said memory cell in said first memory state, and wherein when said memory cell is in said second state, said body region does not turn on said silicon controlled rectifier device, current does not flow, and a blocking operation results, causing said body to maintain said second memory state.

19. The method of claim 18, wherein said memory cell includes, in addition to said substrate terminal, a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate; and

a buried well terminal electrically connected to said buried layer;

said method further comprising;

applying a substantially neutral voltage to said bit line terminal;

applying a negative voltage to said word line terminal; and

allowing said source line terminal and said buried well terminal to float.

20. The method of claim 18, wherein said memory cell includes, in addition to said substrate terminal, a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate; and

a buried well terminal electrically connected to said buried layer;

said method further comprising;

applying a substantially neutral voltage to said source line terminal;

applying a negative voltage to said word line terminal; and

allowing said bit line terminal and said buried well terminal to float.

21. A method of reading the data state of a semiconductor dynamic random access memory cell, wherein said memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

a second region having said second conductivity type, said second region being spaced apart from said first region;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; and

a gate positioned between said first and second regions and adjacent said body region;

wherein said memory cell further comprises a substrate terminal electrically connected to said substrate, a source line terminal electrically connected to one of said first and second regions, a bit line terminal electrically connected to the other of said first and second regions, a word line terminal connected to said gate, and a buried well terminal electrically connected to said buried layer;

wherein each said memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration, said method comprising;

applying a positive voltage to said substrate terminal;

applying a positive voltage to said word line terminal; and

applying a substantially neutral voltage to said bit line terminal; and

allowing voltage levels of said source line terminal and said buried well terminal to float;

wherein, when said memory cell is in said first data state, a silicon controlled rectifier device is formed by said substrate, buried well, body region and region connected to said bit line terminal is in low-impedance, conducting mode, and a higher cell current is observed at said bit line terminal compared to when said memory cell is in said second data state, as when said memory cell is in said second data state, said silicon rectifier device is in blocking mode.