Digital signal processing apparatus

• US 8,077,768 B2
• Filed: 02/13/2007
• Issued: 12/13/2011
• Est. Priority Date: 02/13/2006
• Status: Active Grant

• Current Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Original Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Inventors: Nakano, Itsuki, Ikeuchi, Akira
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): TAYONG, HELENE E
• Application Number:
  US11/705,686
• Publication Number:
  US 20070189400A1
• Time in Patent Office: 1,764 Days
• Field of Search: 375/239, 327/1, 327/100, 329/313, 332/112, 370/205, 370/213
• US Class Current: 375/239
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/3828 using current integration
• CPC Class Codes: H03H 17/0671 Cascaded integrator-comb [CIC] filters
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/462 Details relating to the decimation process decimation filters in general H03H17/0416, H03H17/0621

Abstract

A digital signal processing apparatus for converting an analog signal to a digital signal and digitally processing the digital signal is disclosed. The apparatus includes a modulation part for performing pulse density modulation on the analog signal and outputting a pulse density modulation signal, a memory for storing a conversion program for converting the pulse density modulation signal to pulse code modulation data, and a CPU for receiving the pulse density modulation signal from the modulation part and converting the received pulse density modulation signal to pulse code modulation data according to the conversion program stored in the memory.

Claims

1. A digital signal processing apparatus for converting an analog signal to a digital signal and digitally processing the digital signal, the apparatus comprising:

a modulation part for performing pulse density modulation on the analog signal and outputting a pulse density modulation signal;

a memory for storing a conversion program for converting the pulse density modulation signal to the pulse code modulation data;

a CPU for receiving the pulse density modulation signal from the modulation part and converting the received pulse density modulation signal to pulse code modulation data according to the conversion program stored in the memory;

wherein the CPU is configured to generate a timer interruption, and

wherein the CPU is configured to obtain the pulse density modulation signal from the modulation part and convert the obtained pulse density modulation signal to the pulse code modulation data when the timer interruption is generated;

a detection part for detecting the analog signal and supplying the analog signal to the modulation part; and

a battery connected to the detection part,

wherein the detection part includes

a voltage detection part for detecting voltage of the battery,

a current detection part for detecting charge current and discharge current of the battery,

a temperature detection part for detecting temperature, and

a selection part for selecting an analog signal output from one of the voltage detection part, the current detection part, and the temperature detection part and supplying the selected analog signal to the modulation part.

2. The digital signal processing apparatus as claimed in claim 1,

wherein the analog signal indicates the charge current and discharge current of the battery,

wherein the memory stores a remaining battery amount calculation program used for calculating the amount of charge remaining in the battery by integrating the charge current and discharge current of the battery, and

wherein the CPU calculates the amount of charge remaining in the battery by integrating the pulse code modulation data of the charge current and discharge current of the battery according to the remaining battery amount calculation program stored in the memory.

3. The digital signal processing apparatus as claimed in claim 1, wherein the modulation part is a sigma-delta converter.

4. The digital signal processing apparatus as claimed in 1, wherein the detection part, the modulation part, the memory, and the CPU are mounted on the same semiconductor integrated circuit apparatus.