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Method and device for three-dimensional path planning to avoid obstacles using multiple planes

  • US 8,078,399 B2
  • Filed: 03/10/2008
  • Issued: 12/13/2011
  • Est. Priority Date: 03/10/2008
  • Status: Expired due to Fees
First Claim
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1. An obstacle-avoidance-processor chip for three-dimensional path planning, the obstacle-avoidance-processor chip comprising:

  • an analog processing circuit communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor, the analog processing circuit configured to construct a three-dimensional obstacle map of an environment based on the received data; and

    at least two analog-resistive-grid networks, configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map, and form a quasi-three-dimensional representation of the environment;

    wherein the obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment.

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