Method for writing to and erasing a non-volatile memory

• US 8,078,796 B2
• Filed: 04/14/2009
• Issued: 12/13/2011
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rudelic, John
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): Nguyen, Nam
• Application Number:
  US12/423,226
• Publication Number:
  US 20100262756A1
• Time in Patent Office: 973 Days
• Field of Search: 711/103, 711/167
• US Class Current: 711/103
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

Claims

1. A computer-implemented method for writing to and erasing a non-volatile memory, the method comprising:

determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period;

slicing a long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

2. The computer-implemented method of claim 1, wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

3. The computer-implemented method of claim 1, wherein the non-volatile memory is a NOR flash memory.

4. The computer-implemented method of claim 1, wherein n is equal to 10, the size of the command window is approximately 72 milliseconds, the time period of one erase slice is approximately 70 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

5. A computer-implemented method for writing to and erasing a non-volatile memory, the method comprising:

dynamically determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period, the dynamically determining based on a dynamic latency erase command;

slicing the dynamic long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period, the dynamic long latency erase command based on an actual state of the non-volatile memory; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

6. The computer-implemented method of claim 5, wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

7. The computer-implemented method of claim 5, wherein the non-volatile memory is a NOR flash memory.

8. The computer-implemented method of claim 5, wherein n is equal to 10, the size of the command window is approximately 52 milliseconds, the time period of one erase slice is approximately 50 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

9. The computer-implemented method of claim 5, wherein n is equal to 10, the size of the command window is approximately 152 milliseconds, the time period of one erase slice is approximately 150 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

10. The computer-implemented method of claim 5, wherein the actual state of the non-volatile memory comprises a small erase backlog, and wherein the dynamic latency erase command is approximately 500 milliseconds.

11. The computer-implemented method of claim 5, wherein the actual state of the non-volatile memory comprises a large erase backlog, and wherein the dynamic latency erase command is approximately 1500 milliseconds.

12. A machine-accessible storage medium having instructions stored thereon which cause a data processing system to perform a method for writing to and erasing a non-volatile memory, the method comprising:

determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period;

slicing a long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

13. The machine-accessible storage medium of claim 12, wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

14. The machine-accessible storage medium of claim 12, wherein the non-volatile memory is a NOR flash memory.

15. The machine-accessible storage medium of claim 12, wherein n is equal to 10, the size of the command window is approximately 72 milliseconds, the time period of one erase slice is approximately 70 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

16. The machine-accessible storage medium of claim 12, wherein determining the size of the command window is performed dynamically and is based on a dynamic latency erase command, wherein slicing the long latency erase command comprises slicing the dynamic long latency erase command, the dynamic long latency erase command based on an actual state of the non-volatile memory.

17. The machine-accessible storage medium of claim 16, wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

18. The machine-accessible storage medium of claim 16, wherein the non-volatile memory is a NOR flash memory.

19. The machine-accessible storage medium of claim 16, wherein n is equal to 10, the size of the command window is approximately 52 milliseconds, the time period of one erase slice is approximately 50 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

20. The machine-accessible storage medium of claim 16, wherein n is equal to 10, the size of the command window is approximately 152 milliseconds, the time period of one erase slice is approximately 150 milliseconds, and the time period of one write operation is approximately 2 milliseconds.