Method and apparatus for caching of page translations for virtual machines

• US 8,078,827 B2
• Filed: 07/05/2007
• Issued: 12/13/2011
• Est. Priority Date: 07/05/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Uhlig, Volkmar, van Doorn, Leendert
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US11/773,747
• Publication Number:
  US 20090013149A1
• Time in Patent Office: 1,622 Days
• Field of Search: None
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 2212/651 Multi-level translation tables

Abstract

A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address to a first guest-physical memory address or an invalid entry, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address to a host-physical memory address or an invalid entry, and managing a cache page table, wherein the cache page table selectively provides a third translation from the guest-virtual memory address to the host-physical memory address, a second guest-physical memory address or an invalid entry.

Claims

1. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for caching of page translations for virtual machines, the method comprising:

managing a plurality of virtual machines having respective guest operating systems and respective guest page tables, wherein a guest page table of a first guest operating system provides a first translation from a first guest-virtual memory address of a translation look-aside buffer miss to a first guest-physical memory address in the guest page table, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address in the guest page table to a host-physical memory address; and

managing a cache page table for each of the virtual machines, the cache page tables storing a plurality of page base addresses, wherein a page base address of the plurality of page base addresses provides a third translation from the first guest-virtual memory address to the host-physical memory address indicated by a host bit associated with the page base address indicating that the page base address denotes a host-physical memory address, and wherein each page base address is associated with a respective host bit indicating whether the respective page base address denotes a guest-physical memory address or a host-physical memory address.

2. The program storage device of claim 1, wherein the cache page table is realized using a cache page table pointer to point to the start of the page table.

3. The program storage device of claim 1, wherein a third translation of another page base address of the plurality of page base addresses is a direct translation from the guest-virtual memory address to the host-physical memory address or an invalid entry, or an indirect translation using the guest page table and the host page table.

4. The program storage device of claim 3, wherein the indirect translation comprises:

reading one or more entries from the guest page table or a processor register; and

translating each entry, if valid, from guest physical memory to host physical memory using the host page table, or if not valid, raise an exception.

5. A method of translating virtual-memory addresses to physical-memory addresses in a computer system serving as a platform for execution of a virtual machine monitor, the method comprising:

managing a plurality of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address of a translation look-aside buffer miss to a first guest-physical memory address, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address in the guest page table to a host-physical memory address of a next level guest page table;

determining that a result of the first translation and the second translation from the guest-virtual to host-physical memory addresses covers a contiguous memory area that spans a plurality of pages of one host memory space;

combining the result of the first translation and the second translation in a single combined translation from the guest-virtual memory address to the host-physical memory address;

inserting the single combined translation as a superpage entry in a first cache page table; and

managing a cache page table for each of the virtual machines, the first cache page table storing the superpage entry, a superpage bit indicating that the superpage entry is stored and at least one status update bit associated with all of the plurality of pages covered by the superpage entry.

6. The method of claim 5, wherein when the at least one status update bit is clear, the processor raises an exception.

7. The method of claim 5, wherein the at least one status update bit comprises an accessed bit and a dirty bit.