Removing local RAM size limitations when executing software code

• US 8,078,842 B2
• Filed: 07/21/2005
• Issued: 12/13/2011
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard, Lesot, Jean-Philippe
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US11/186,036
• Publication Number:
  US 20060026412A1
• Time in Patent Office: 2,336 Days
• Field of Search: 712/226
• US Class Current: 712/211
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.

Claims

1. An electronic device, comprising:

a processor configured to directly execute at least some bytecodes in an instruction set of the processor, the processor comprising;

decode logic;

a vector table comprising a plurality of entries, wherein each entry of the plurality of entries corresponds to a bytecode in the instruction set and each entry comprises;

a first field for indicating whether a micro-sequence is to be executed instead of the corresponding bytecode; and

a second field for storing a reference to the micro-sequence; and

an instruction memory configured to store micro-sequences referenced by the entries in the vector table; and

a memory externally coupled to the processor, wherein the memory is configured to store a group of instructions that is to be executed instead of a bytecode,

wherein the decode logic is configured to;

use a bytecode to locate an entry of the vector table corresponding to the bytecode; and

cause a micro-sequence referenced in the second field of the entry to be executed when the first field of the entry indicates that a micro-sequence is to be executed instead of the bytecode,

wherein, when executed, the micro-sequence causes the processor to execute the group of instructions.

2. The electronic device of claim 1, wherein, when executed, the group of instructions performs a function of the bytecode.

3. The electronic device of claim 1, wherein execution of the micro-sequence causes the processor to push onto a stack information pertaining to a state of the processor.

4. The electronic device of claim 3, wherein the information pertaining to the state of the processor comprises only a minimum amount of information needed to resume execution of one of the micro-sequence and a bytecode following the bytecode.

5. The electronic device of claim 3, wherein the processor, after executing the group of instructions and prior to resuming execution of one of the micro-sequence and a bytecode following the bytecode, pops the information off the stack and stores at least some of the information to registers in the processor.

6. The electronic device of claim 1, wherein the electronic device is at least one of a wireless communication device or a battery-operated device.

7. The electronic device of claim 1, wherein the processor uses a same program counter when executing the bytecode, a bytecode following the bytecode, and the group of instructions and another program counter when executing the micro-sequence.

8. A processor configured to directly execute at least some bytecodes in an instruction set of the processor, the processor comprising:

decode logic;

a vector table comprising a plurality of entries, wherein each entry of the plurality of entries corresponds to a bytecode in the instruction set and each entry comprises;

a first field for indicating whether a micro-sequence is to be executed instead of the corresponding bytecode; and

a second field for storing a reference to the micro-sequence; and

an instruction memory configured to store micro-sequences referenced by the entries in the vector table,

wherein the decode logic is configured to;

use a bytecode to locate an entry of the vector table corresponding to the bytecode; and

cause a micro-sequence referenced in the second field of the entry to be executed when the first field of the entry indicates that a micro-sequence is to be executed instead of the bytecode,

wherein, when executed, the micro-sequence causes the processor to execute a group of instructions stored in a memory external to the processor, and

wherein execution of the micro-sequence causes the decode logic to push onto a stack data pertaining to a state of the processor.

9. The processor of claim 8, wherein, when executed, the group of instructions performs a function of the bytecode.

10. The processor of claim 8, wherein, prior to a bytecode following the bytecode, the decode logic pops the data off the stack and stores at least some of the data to registers in the processor.

11. The processor of claim 8, wherein the data consists of two program counters and a status of the processor.

12. The processor of claim 8, wherein the data comprises only a minimum amount of information needed to resume execution of one of the micro-sequence and a bytecode following the bytecode.

13. The processor of claim 12, wherein said minimum amount of information comprises only contents of three registers.

14. A method comprising:

using a bytecode to locate an entry corresponding to the bytecode in a vector table, wherein the vector table comprises an entry for each bytecode in an instruction set of a processor;

causing a micro-sequence referenced in a second field of the entry to be executed when a first field in the entry indicates that the micro-sequence is to be executed by the processor instead of executing the bytecode,

wherein the micro-sequence is stored in an instruction memory comprised in the processor,

wherein, when executed, the micro-sequence causes the processor to execute a group of instructions stored in a memory external to the processor, and

wherein execution of the micro-sequence causes registers pertaining to a state of the processor to be pushed onto a stack before the group of instructions is executed.

15. The method of claim 14, wherein the registers comprise two program counters and a status of the processor.

16. The method of claim 14, wherein, when executed, the group of instructions performs a function of the bytecode.