Memory controller having front end and back end channels for modifying commands

• US 8,078,848 B2
• Filed: 01/09/2009
• Issued: 12/13/2011
• Est. Priority Date: 01/09/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US12/351,206
• Publication Number:
  US 20100180105A1
• Time in Patent Office: 1,068 Days
• Field of Search: None
• US Class Current: 712/225
• CPC Class Codes: G06F 13/1631 through address comparison
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands.

Claims

1. A memory controller, comprising:

a back end channel, wherein the back end channel includes;

a command queue configured to hold commands; and

circuitry configured to;

modify at least a number of commands in the queue; and

execute the modified commands; and

a front end channel, wherein the front end channel includes circuitry configured to;

receive commands from a host;

send commands to the back end channel; and

perform a number of functions selected from the group of functions including;

changing the order in which the commands are sent to the back end channel;

combining a number of combinable commands received from the host into a command; and

deleting a command received from the host which will be overwritten by an other command received from the host.

2. The memory controller of claim 1, wherein circuitry configured to modify at least a number of commands comprises circuitry configured to modify the number of commands while they are held in the queue.

3. The memory controller of claim 1, wherein circuitry configured to modify at least a number of commands comprises circuitry configured to change an order in which commands in the queue are held in the queue.

4. The memory controller of claim 3, wherein circuitry configured to execute the modified commands comprises circuitry configured to execute commands in the queue according to the changed order.

5. The memory controller of claim 1, wherein the circuitry of the back end channel is further configured to determine whether commands in the queue can be modified.

6. The memory controller of claim 1, wherein circuitry configured to modify at least a number of commands comprises at least one of:

circuitry configured to modify a number of commands in the queue if the number of commands in the queue can be combined into a command;

or

circuitry configured to modify a number of commands in the queue if the number of commands in the queue will be overwritten by another command in the queue.

7. The memory controller of claim 6, wherein circuitry configured to modify a number of commands in the queue if the number of commands in the queue can be combined into a command comprises circuitry configured to modify a number of commands in the queue if the number of commands in the queue can be combined into a single command.

8. The memory controller of claim 6, wherein circuitry configured to modify a number of commands in the queue if the number of commands in the queue can be combined into a command comprises at least one of:

circuitry configured to combine a number of overlapping commands into a command;

or

circuitry configured to combine a number of sequential commands into a command.

9. The memory controller of claim 6, wherein circuitry configured to modify a number of commands in the queue if the number of commands in the queue will be overwritten by another command in the queue comprises circuitry configured to:

determine whether a command in the queue will be overwritten by an other command in the queue; and

delete the command that will be overwritten by the other command.

10. The memory controller of claim 1, wherein the circuitry of the back end channel includes at least one of:

a processor;

or

an application-specific integrated circuit.

11. A memory controller, comprising:

a back end channel, wherein the back end channel includes;

a command queue configured to hold a number of commands; and

a processor configured to perform a number of functions selected from the group of functions including;

changing an order in which commands are held in the queue;

combining a number of combinable commands in the queue into a command; and

deleting a command in the queue which will be overwritten by an other command in the queue; and

a front end channel, wherein the front end channel includes;

a command dispatcher configured to;

receive a number of commands from a host; and

send a number of commands to the back end channel; and

a command processor configured to perform a number of functions selected from the group of functions including;

changing the order in which the command dispatcher sends commands to the back end channel;

combining a number of combinable commands received by the command dispatcher from the host into a command; and

deleting a command received by the command dispatcher from the host which will be overwritten by an other command received by the command dispatcher from the host.

12. The memory controller of claim 11, wherein the processor of the back end channel comprises a processor configured to perform one or more functions selected from the group of functions.

13. The memory controller of claim 11, wherein combinable commands include:

overlapping commands; and

sequential commands.

14. The memory controller of claim 11, wherein:

the queue is configured to hold commands in the order in which the command dispatcher sends the commands to the back end channel.

15. The memory controller of claim 11, wherein the queue is configured to hold a number of commands equal to a number of commands that can be held by the command dispatcher.

16. The memory controller of claim 11, wherein the command dispatcher is configured to:

send the commands to the back end channel in the order in which the command dispatcher receives the commands from the host.

17. The memory controller of claim 11, wherein the command processor is configured to perform the number of functions when the command dispatcher is unable to receive commands from the host.

18. The memory controller of claim 17, wherein the command processor is configured to perform the number of functions when the command dispatcher is full.

19. The memory controller of claim 11, wherein:

the command processor is configured to;

determine whether the functions in the group of functions configured to be performed by the processor of the back end channel are not to be performed on commands held in the command dispatcher; and

mark commands held in the command dispatcher that are not to have the functions in the group of functions configured to be performed by the processor of the back end channel performed on them.

20. The memory controller of claim 19, wherein the processor of the back end channel is configured to not perform the functions in the group of functions on marked commands.

21. A method for operating a memory device, comprising:

modifying a number of commands held in a queue in a back end channel, wherein modifying the number of commands includes performing a number of the functions selected from the group of functions including;

changing an order in which commands are held in the queue;

combining a number of combinable commands in the queue into a command; and

deleting a command in the queue which will be overwritten by an other command in the queue;

executing the modified commands according to an order in which the modified commands are held in the queue;

receiving, by circuitry of a front end channel, commands from a host;

sending, by the circuitry of the front end channel, commands to the back end channel; and

performing, by the circuitry of the front end channel, a number of functions selected from the group of functions including;

changing the order in which the commands are sent to the back end channel;

combining a number of combinable commands received from the host into a command; and

deleting a command received from the host which will be overwritten by an other command received from the host.

22. The method of claim 21, wherein:

changing an order in which commands are held in the queue includes ordering the commands in an order in which they are to be executed; and

executing the modified commands according to an order in which the modified commands are held in the queue includes executing the commands according to the order in which they are to be executed.

23. The method of claim 21, wherein combining a number of combinable commands in the queue into a command includes combining a number of combinable commands in the queue into a single command.

24. The method of claim 21, wherein combining a number of combinable commands includes:

combining overlapping commands; and

combining sequential commands.

25. The method of claim 21, wherein the method includes:

receiving additional commands in the queue while the modified commands are being executed; and

modifying the additional commands while the modified commands are being executed.

26. The method of claim 21, wherein executing the modified commands includes executing the modified commands to operate on a memory array.

27. A method for operating a memory device, comprising:

combining a number of combinable commands held in a queue of a back end channel into a command, thereby avoiding a partial page programming operation;

receiving, by a command dispatcher of a front end channel, a number of commands from a host;

sending, by the command dispatcher of the front end channel, a number of commands to the back end channel; and

performing, by a command processor of the front end channel, a number of functions selected from the group of functions including;

changing the order in which the command dispatcher sends commands to the back end channel;

combining a number of combinable commands received by the command dispatcher from the host into a command; and

deleting a command received by the command dispatcher from the host which will be overwritten by an other command received by the command dispatcher from the host.

28. The method of claim 27, wherein each of the number of combinable commands held in the queue is associated with a portion of a particular page of memory cells.

29. The method of claim 27, further comprising executing the command combined from the number of combinable commands held in the queue.