Self aligned contact in a semiconductor device and method of fabricating the same

• US 8,080,459 B2
• Filed: 06/15/2004
• Issued: 12/20/2011
• Est. Priority Date: 09/24/2002
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Xu, Robert Q.
• Primary Examiner(s): Blum, David S
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US10/869,382
• Publication Number:
  US 20050224891A1
• Time in Patent Office: 2,744 Days
• Field of Search: 257/382, 257/412, 257/330, 257/332, 257/E21.585, 257/E29.201, 257/E29.154, 257/331, 257/E29.257, 257/E29.26, 257/E29.262, 438/299, 438/589, 438/242, 438/246, 438/259, 438/280, 438/270, 438/271
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.

Claims

1. A method of fabricating a self aligned contact in a semiconductor device comprising:

etching a trench in a core area and partially extending into a termination area of a substrate;

growing a first oxide on said substrate proximate a wall and a bottom of said trench;

depositing a polysilicon layer in said core area and said termination area;

selectively etching said polysilicon layer to form a gate region in said core area portion of said trench, a first portion of a gate interconnect region in said termination area portion of said trench, and a second portion of said gate interconnect region in said termination area outside of said trench; and

selectively doping a periphery structure portion of said polysilicon layer in said termination area before said selectively etching said polysilicon layer.

2. The method according to claim 1, further comprising:

growing a second oxide layer on said substrate prior to said etching said trench; and

depositing a first nitride layer on said second oxide layer prior to said etching said trench.

3. The method according to claim 2, further comprising:

depositing a dielectric layer on said selectively etched polysilicon layer and said first nitride layer; and

selectively etching said dielectric layer to form a gate insulator region about said gate region and said gate interconnect region from said first oxide layer and said dielectric layer.

4. The method according to claim 3, further comprising:

removing said first nitride layer in said core area after etching-back said dielectric layer;

implanting a body region in an upper portion of said substrate proximate said trench after removing said nitride layer; and

implanting a source region in a portion of said body region proximate said gate region after removing said nitride layer.

5. The method according to claim 4, further comprising:

depositing a second nitride layer after implanting said body region and said source region;

etching a source/body contact opening through said second nitride layer, said source region and a portion of said body region;

etching a gate contact opening through said second nitride layer in said termination area, wherein a portion of said gate interconnect region is exposed;

forming a source/body contact extending down through said source/body contact opening to said source region and said body region in said core area; and

forming a gate contact extending down through said gate contact opening to said second portion of said gate interconnect region in said termination area.

6. The method according to claim 1, wherein said selectively etching said polysilicon layer comprises forming said periphery structure from said polysilicon layer in said termination area.

7. A method of fabricating a trench metal-oxide-semiconductor field effect transistor comprising:

depositing a sacrificial oxide layer on a substrate;

depositing a first nitride layer on said sacrificial oxide layer;

etching a trench through said first nitride layer and said sacrificial oxide layer and into a core area and partially extending into a termination area of said substrate;

growing a first portion of a gate insulator region on said substrate proximate a walls and bottom of said trench to form a first portion of a gate insulator region;

depositing a polysilicon layer in said core area and said termination area including said trench;

etching-back said polysilicon to form a gate region in said core area portion of said trench, a first portion of a gate interconnect region in said termination area portion of said trench, and a second portion of said gate interconnect region in said termination area outside of said trench;

depositing a dielectric layer on said gate region, gate interconnect region and said first nitride layer;

etching-back said dielectric layer to form a second portion of said gate insulator region about said gate region and said gate interconnect region;

removing said first nitride layer in said core area;

implanting a body region in an upper portion of said substrate in said core area proximate said gate region to form a drain region in a lower portion of said substrate in said core area; and

implanting a source region in said body region in said core area proximate said gate region, wherein said source region is separated from said drain region by said body region.

8. The trench metal-oxide-semiconductor field effect transistor according to claim 7, further comprising:

etching a source/body contact opening in said core area and a gate contact opening in said termination area;

forming a source/body contact extending down through said source/body contact opening to said source region and said body region from a first metal layer; and

forming a gate contact extending down through said gate contact opening to said gate interconnect region from said second metal layer.

9. The method according to claim 8, wherein:

said etching said trench further forms a periphery trench in said termination area;

said etching-back said polysilicon layer further forms a first electrode of a field capacitor in said periphery trench; and

further comprising

forming a second electrode of said field capacitor from said first metal layer when forming said source/body contact and said gate contact.

10. The method according to claim 7, further comprising selectively implanting said substrate proximate said bottom of said trench before said depositing said polysilicon layer.

11. The method according to claim 7, further comprising

implanting a portion of said polysilicon layer in said termination area to form a diode in a portion of said gate interconnect region.

12. The method according to claim 7, wherein said etching-back said polysilicon layer further forms a temperature cell in said termination area.

13. A method of fabricating a self aligned contact in a semiconductor device comprising:

etching a trench in a core area and partially extending into a termination area of a substrate;

growing a first oxide on said substrate proximate a wall and a bottom of said trench;

depositing a polysilicon layer in said core area and said termination area;

selectively etching said polysilicon layer to form a gate region in said core area portion of said trench, a first portion of a gate interconnect region in said termination area portion of said trench, and a second portion of said gate interconnect region in said termination area outside of said trench;

implanting a body region in a portion of said substrate in said core area proximate said gate region; and

implanting a source region in a portion of said body region in said core area proximate said gate region gate region.

14. The method according to claim 13, further comprising:

depositing a dielectric layer on said selectively etched polysilicon layer and said first nitride layer; and

selectively etching said dielectric layer to form a gate insulator region about said gate region and said gate interconnect region from said first oxide layer and said dielectric layer.

15. The method according to claim 14, further comprising:

growing a second oxide layer on said substrate prior to said etching said trench; and

depositing a first nitride layer on said second oxide layer prior to said etching said trench.

16. The method according to claim 15, further comprising:

removing said first nitride layer in said core area after etching-back said dielectric layer;

implanting said body region after removing said nitride layer; and

implanting said source region after removing said nitride layer.

17. The method according to claim 16, further comprising:

depositing a second nitride layer after implanting said body region and said source region;

etching a source/body contact opening through said second nitride layer, said source region and a portion of said body region;

etching a gate contact opening through said second nitride layer in said termination area, wherein a portion of said gate interconnect region is exposed;

forming a source/body contact extending down through said source/body contact opening to said source region and said body region in said core area; and

forming a gate contact extending down through said gate contact opening to said second portion of said gate interconnect region in said termination area.

18. The method according to claim 17, further comprising:

forming a periphery structure from said polysilicon layer in said termination area by said selectively etching said polysilicon layer; and

selectively doping said periphery structure portion of said polysilicon layer in said termination area before said selectively etching said polysilicon layer.