Flash memory device with redundant columns

• US 8,081,511 B2
• Filed: 10/05/2010
• Issued: 12/20/2011
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Han, Jin-Man, Yip, Aaron
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US12/898,070
• Publication Number:
  US 20110019474A1
• Time in Patent Office: 441 Days
• Field of Search: 365/185.09, 365/185.11, 365/189.02, 365/189.05, 365/200, 365/230.03, 365/230.04
• US Class Current: 365/185.09
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Claims

1. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and third and fourth redundancy interleave groups of redundant columns;

first and second data latches configured to store data read from the first and second interleave groups of regular columns, respectively;

third and fourth redundant data latches configured to store data read from the third and fourth redundancy interleave groups of redundant columns, respectively;

a multiplexer comprising at least four inputs, each of which is electrically coupled to a respective one of the first and second data latches and the third and fourth redundant data latches; and

a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme.

2. The apparatus of claim 1, wherein the apparatus is configured to map a column address of at least one regular column in the first interleave group to a redundant column in the third or fourth redundancy interleave group.

3. The apparatus of claim 1, wherein the plurality of columns further comprise fifth and sixth interleave groups of regular columns and seventh and eighth redundancy interleave groups of redundant columns.

4. The apparatus of claim 3, wherein the apparatus is configured to map a column address of at least one regular column in the first interleave group to a redundant column in the seventh or eighth redundancy interleave group.

5. The apparatus of claim 1, further comprising a redundancy selector configured to select a redundant column at least partly in response to the column address of a regular column.

6. The apparatus of claim 5, wherein the redundancy selector comprises:

a plurality of column redundancy elements, each of the column redundancy elements being configured to receive a column address of a regular column and a programmed address, the programmed address indicating a defective regular column, and to output a redundancy signal indicative of whether the column address and the programmed address match each other; and

a first logic gate configured to perform an OR operation on the redundancy signals from the plurality of column redundancy elements, and to output a redundancy hit signal.

7. The apparatus of claim 6, further comprising an interleave group selector configured to provide the multiplexer with one or more control signals to allow the multiplexer to alternately output data from the data latches.

8. The apparatus of claim 6, wherein each of the column redundancy elements comprises a plurality of second logic gates and a third logic gate, each of the second logic gates being configured to perform an XNOR operation on a respective one bit of the column address and a respective one bit of the programmed address, and to provide an output to the third logic gate, the third logic gate being configured to perform an AND operation on the outputs from the second logic gates, and to output one of the redundancy signals.

9. The apparatus of claim 1, wherein the apparatus is configured to switch among two or more of one-way, two-way, and four-way interleaved read schemes.

10. The apparatus of claim 1, wherein the apparatus is configured to perform an interleaved read scheme having a same number of ways as a number of the interleave groups when a number of defective columns in each of the interleave groups is equal to or less than a number of redundant columns in a respective one of the redundancy interleave groups.

11. The apparatus of claim 1, wherein the apparatus is configured to perform an interleaved read scheme having a lower number of ways than a number of the interleave groups when a number of defective columns in any of the interleave groups exceeds a number of redundant columns in a respective one of the redundancy interleave groups.

12. An electronic device, comprising:

a memory block comprising a regular section and a repair section, wherein the regular section further comprises even-numbered columns and odd-numbered columns alternating with each other, wherein the repair section further comprises even-numbered redundant columns and odd-numbered redundant columns alternating with each other;

a first data latch electrically coupled to the even-numbered columns, but not to the odd-numbered columns, in the regular section;

a second data latch electrically coupled to the odd-numbered columns, but not to the even-numbered columns, in the regular section;

a first redundant data latch electrically coupled to the even-numbered redundant columns, but not to the odd-numbered redundant columns, in the repair section;

a second redundant data latch electrically coupled to the odd-numbered redundant columns, but not to the odd-numbered columns, in the repair section;

a multiplexer comprising first to fourth inputs electrically coupled to the first data latch, the second data latch, the first redundant data latch, and the second redundant data latch, respectively; and

a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme.

13. The device of claim 12, wherein the first data latch is positioned on an opposite side of the memory block from the second data latch, and wherein the first redundant data latch is positioned on an opposite side of the memory block from the second redundant data latch.

14. The device of claim 12, wherein the memory block further comprises a plurality of word lines, each of which crosses the even-numbered and odd-numbered columns and the even-numbered and odd-numbered redundant columns.

15. The device of claim 12, further comprising:

a first redundancy selector configured to provide control signals to one or more of the first redundancy latch and the multiplexer at least partly in response to a column address;

a second redundancy selector configured to provide control signals to one or more of the second redundancy latch and the multiplexer at least partly in response to the column address; and

an interleave group selector configured to provide control signals to one or more of the first data latch, the second data latch, and the multiplexer at least partly in response to one or more of the column address and the control signals from the first and second redundancy selectors.

16. The device of claim 12, wherein the device is configured to switch among two or more of one-way, two-way, and four-way interleaved read schemes.

17. A method of reading data from a flash memory device comprising a memory block, wherein the memory block includes a plurality of rows and a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and first and second redundancy interleave groups of redundant columns, each of the rows comprising a word line coupled to a respective row of the memory cells, the method comprising:

latching a first set of data digits that are sequentially read from the first interleave group of regular columns in the memory block;

latching a second set of data digits that are sequentially read from the second interleave group of regular columns in the memory block;

latching a data digit from a redundant column in the first redundancy interleave group of redundant columns in the memory block, the redundant column being configured to replace a defective column in the first interleave group of regular columns;

outputting the latched first and second sets of data digits via first and second lines, respectively, to a multiplexer;

outputting the latched data digit from the redundant column via a third line to the multiplexer; and

outputting the first and second sets of data digits in an alternating manner from the multiplexer while outputting the data digit from the redundant column from the multiplexer between two immediately subsequent data digits in the second set.

18. The method of claim 17, further comprising:

latching a data digit from an other redundant column in the second redundancy interleave group of redundant columns in the memory block, the other redundant column being configured to replace an other defective column in the first interleave group of regular columns;

outputting the latched data digit from the other redundant column via a fourth line to the multiplexer; and

outputting the data digit from the other redundant column from the multiplexer between two immediately subsequent data digits in the second set.

19. The method of claim 17, wherein the method comprises performing one interleaved read scheme selected from a plurality of interleaved read schemes, based on whether a number of defective columns in each of the interleave groups exceeds a number of redundant columns in a respective one of the redundancy interleave groups.

20. The method of claim 17, wherein the method comprises performing an interleaved read scheme having a lower number of ways than a number of the interleave groups when a number of defective columns in any of the interleave groups exceeds a number of redundant columns in a respective one of the redundancy interleave groups.