Representing a plurality of instructions with a fewer number of micro-operations

• US 8,082,430 B2
• Filed: 08/09/2005
• Issued: 12/20/2011
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Valentine, Robert, Anati, Ittai, Sperber, Zeev, Ouziel, Ido, Pribush, Gregory, Leibovitz, Amir
• Primary Examiner(s): Alrobaye, Idriss N
• Application Number:
  US11/200,777
• Publication Number:
  US 20070038844A1
• Time in Patent Office: 2,324 Days
• Field of Search: 712/208, 712/E9.054, 712/219
• US Class Current: 712/245
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.

Claims

1. An apparatus comprising:

at least two decoders to decode at least two instructions into at least two micro-operations (uops);

a storage unit to store the at least two uops;

uop fusion logic to fuse the at least two uops into a single fused uop that is to represent the complete function of the at least two uops, wherein the at least two uops are to be fused into the single fused uop in response to a determination that the at least two uops are compatible for fusion, wherein;

two or more uops are considered to be compatible for fusion if an output of one uop is to source one or more uops to be fused;

registers accessed by the two or more uops are compatible if they have the same destination register for the two or more uops;

flag destinations of the two or more uops are compatible if both of uops overwrite the same flag;

source operands of the two or more uops are compatible if operands from both of the uops do not overflow the available registers to store the source operands; and

the at least two instructions are adjacent to each other in program order;

execution logic to process the fused uop without unfusing the fused uop; and

determination logic to determine whether processing of the fused uop results in a trap, assist, or fault condition, wherein if no trap, assist, or fault condition occurs, the fused uop is retired.

2. The apparatus of claim 1 wherein a destination storage location of a result of executing a first one of the plurality of instructions is a source storage location of an operand of a second one of the plurality of instructions.

3. The apparatus of claim 2 wherein the first and second one of the plurality of instructions are adjacent to each other in program order.

4. The apparatus of claim 2 wherein the first and second one of the plurality of instructions are non-adjacent to each other in program order.

5. The apparatus of claim 2 wherein the single fused uop is to be retired in an order to maintain correct state within a processor in which the single fused uop is to be executed.

6. The apparatus of claim 1 further comprising a reservation station to store operands, memory offsets, and branch targets associated with the single fused uop.

7. The apparatus of claim 6 further comprising an execution unit to execute the single fused uop.

8. The apparatus of claim 7 further comprising a retirement unit to commit state information resulting from executing the single fused uop to machine state.

9. A system comprising:

a memory unit to store two or more instructions to be represented by one micro-operation (uop);

at least two decode logics to decode the two or more instructions into at least two or more uops;

a first logic to cause representation of the two or more instructions by a single fused uop that is to represent the complete function of the at least two uops, wherein the two or more instructions are to be decoded by the decode logics, wherein the single fused uop corresponds to one of a plurality of operations into which the two or more instructions are to be decoded and wherein the single fused uop is to be generated in response to a determination that at least two uops, corresponding to the single fused uop, are compatible for fusion, wherein;

two or more uops are considered to be compatible for fusion if an output of one uop is to source one or more uops to be fused;

registers accessed by the two or more uops are compatible if they have the same destination register for the two or more uops;

flag destinations of the two or more uops are compatible if both of uops overwrite the same flag;

source operands of the two or more uops are compatible if operands from both of the uops do not overflow the available registers to store the source operands; and

the two or more instructions are adjacent to each other in program order;

execution logic to process the single fused uop without unfusing the fused uop; and

determining whether processing of the fused uop results in a trap, assist, or fault condition and if no trap, assist, or fault condition occurs the fused uop is to be retired.

10. The system of claim 9 further comprising a processor to execute the single fused uop and retire the single fused uop such that correct processor state is maintained.

11. The system of claim 9 further comprising an audio I/O coupled to the memory unit.

12. The system of claim 10 wherein the processor comprises an instruction queue to store the two or more instructions adjacently to each other before being decoded by the decode logics.

13. The system of claim 10 wherein the processor comprises an instruction queue to store the two or more instructions non-adjacently to each other before being decoded by the decode logics.

14. The system of claim 9 wherein the two or more instructions comprise a first instruction to compare two operands and a second instruction to change an instruction pointer in response to the result of the compare of the two operands.

15. The system of claim 9 wherein the two or more instructions comprise a first instruction to generate a sum of a first and second operand and a second instruction to compare the sum with a third operand.

16. The system of claim 9 wherein the first logic comprises at least one instruction, which when executed by a processor causes the processor to determine whether the two or more instructions are to be represented by a single fused uop.

17. A method comprising:

decoding, at two decoders, two or more instructions into at least two micro-operations (uops);

storing the at least two uops in a storage unit;

fusing, at a uop fusion logic, the at least two uops into a single fused uop that is to represent the complete function of the at least two uops, wherein the at least two uops are to be fused into the single fused uop in response to a determination that the at least two uops are compatible for fusion, wherein;

two or more uops are considered to be compatible for fusion if an output of one uop is to source one or more uops to be fused;

registers accessed by the two or more uops are compatible if they have the same destination register for the two or more uops;

flag destinations of the two or more uops are compatible if both of uops overwrite the same flag;

source operands of the two or more uops are compatible if operands from both of the uops do not overflow the available registers to store the source operands; and

the two or more instructions are adjacent to each other in program order;

processing, at an execution logic, the fused uop without unfusing the fused uop; and

determining, at a determination logic, whether processing of the fused uop results in a trap, assist, or fault condition, wherein if no trap, assist, or fault condition occurs, the fused uop is retired.

18. The method of claim 17, further comprising examining a relationship between a source operand storage location of a first one of the two or more instructions and a result destination storage location of a second one of the two or more instructions.

19. The method of claim 17, further comprising reordering the single fused uop in relation to other uops whose execution are to result in an incorrect machine state.

20. The method of claim 19, further comprising calling a service routine to generate correct machine state if the execution of the single fused uop is to result in a condition chosen from a group comprising:

a fault, an assist, and a trap.

21. The method of claim 20, wherein the service routine is to use state information resulting from the execution of uop immediately before the single fused uop.

22. The method of claim 20, wherein the service routine uses state information resulting from execution of the single fused uop.

23. The method of claim 20, wherein the service routine uses state information resulting from the execution of a uop corresponding to the first in program order of the two or more instructions.

24. A non-transitory machine-readable medium having stored thereon a set of instructions, which if executed by a machine cause the machine to:

decode two or more instructions into at least two micro-operations (uops);

store the at least two uops;

fuse the at least two uops into a single fused uop that is to represent the complete function of the at least two uops, wherein the at least two uops are to be fused into the single fused uop in response to a determination that the at least two uops are compatible for fusion, wherein;

two or more uops are considered to be compatible for fusion if an output of one uop is to source one or more uops to be fused;

registers accessed by the two or more uops are compatible if they have the same destination register for the two or more uops;

flag destinations of the two or more uops are compatible if both of uops overwrite the same flag;

source operands of the two or more uops are compatible if operands from both of the uops do not overflow the available registers to store the source operands; and

the two or more instructions are adjacent to each other in program order;

process the fused uop without unfusing the fused uop; and

determine whether processing of the fused uop results in a trap, assist, or fault condition, wherein if no trap, assist, or fault condition occurs, the fused uop is retired.

25. The machine-readable medium of claim 24, wherein if one of the conditions occurred as a result of executing operations corresponding to a first of the two or more instructions and not a second of the two or more instructions, causing the machine to store machine state resulting from operations corresponding to the first of the two or more instructions.

26. The machine-readable medium of claim 24, wherein if one of the conditions occurred as a result of executing operations corresponding to a second of the two or more instructions, causing the machine to store machine state resulting from operations corresponding to the second of the two or more instructions.

27. The machine-readable medium of claim 24, wherein if one of the conditions occurred as a result of executing operations corresponding to a first instruction and a second instruction of the two or more instructions, causing the machine to perform the first and second instructions individually instead of performing the single uop.

28. The machine-readable medium of claim 24, further comprising causing the machine to retire a first and second instruction of the two or more instructions after storing the machine state.