System for performing error correction operations in a memory hub device of a memory module

• US 8,082,482 B2
• Filed: 08/31/2007
• Issued: 12/20/2011
• Est. Priority Date: 08/31/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US11/848,349
• Publication Number:
  US 20090063922A1
• Time in Patent Office: 1,572 Days
• Field of Search: 714/763, 714/764, 714/768, 714/718, 714/E11.034, 365/201
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices. The memory hub device also comprises second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices, wherein the memory hub device transmit and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel; and

first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices; and

second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices, wherein data read out of the set of memory devices, thereby forming read data, includes a first error correction codeword previously generated for the data, wherein the second error correction logic generates check bits based on the read data and the first error correction codeword in the read data, the check bits indicating if the read data is correct, and wherein if the second error correction logic determines that the read data contains errors that are not correctable, then the read data is output from the memory hub device to the external memory controller along with an error signal indicating the read data to be invalid.

2. The memory system of claim 1, wherein the memory hub device further comprises first error correction code generation logic that generates error correction code data based on write data received from the external memory controller via the link interface.

3. The memory system of claim 1, wherein the second error correction logic comprises logic that corrects the read data received from the set of memory devices prior to transmitting the read data to the external memory controller via the link interface.

4. The memory system of claim 1, wherein, in response to receiving a read access request from the external memory controller, the memory hub controller responds by driving memory devices in the set of memory devices using a memory device address and control bus to read out data from the set of memory devices, and wherein the read data is provided to the second error correction logic.

5. The memory system of claim 1, wherein if the second error correction logic is able to be corrected, then the second error correction logic generates pointers to correct data for bits of the read data that are determined to be incorrect.

6. The memory system of claim 1, wherein, in response to receiving a write access request from the external memory controller, write data associated with the write access request is provided to first error correction code generation logic of the memory hub controller, and wherein the first error correction code generation logic generates the first error correction codeword based on the write data and adds the first error correction codeword to the write data thereby forming modified write data.

7. The memory system of claim 6, wherein the modified write data having the first error correction codeword is sent to the set of memory devices via the memory device data interface under control of the memory hub controller.

8. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

9. The memory system of claim 1, wherein the memory module is part of a data processing device.

10. The memory system of claim 1, wherein the memory module is part of a main memory of a data processing system.

11. The memory system of claim 1, wherein the second error correction logic stores the read data in a read data queue along with a tag indicating the read data to be invalid if the second error correction logic determines that the read data contains an error that is not correctable by the second error correction logic.

12. The memory system of claim 1, wherein the memory hub device further comprises second error correction code generation logic in the read logic integrated in the memory hub device, and wherein the second error correction code generation logic generates a second error correction codeword that is added to the read data before transmitting the read data to the external memory controller via the link interface responsive to the external memory controller expecting to receive the read data with an error correction codeword.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices, wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel; and

first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path, for writing data to the set of memory devices; and

second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices, wherein data read out of the set of memory devices, thereby forming read data, includes a first error correction codeword previously generated for the data, wherein the second error correction logic generates check bits based on the read data and the first error correction codeword in the read data, the check bits indicating if the read data is correct, and wherein if the second error correction logic determines that the read data contains errors that are not correctable, then the read data is output from the memory hub device to the external memory controller along with an error signal indicating the read data to be invalid.

14. The data processing system of claim 13, wherein memory hub device further comprises first error correction code generation logic that generates error correction code data based on write data received from the external memory controller via the link interface.

15. The data processing system of claim 13, wherein the second error correction logic comprises logic that corrects the read data received from the set of memory devices prior to transmitting the read data to the external memory controller via the link interface.

16. The data processing system of claim 13, wherein, in response to receiving a read access request from the external memory controller, the memory hub controller responds by driving memory devices in the set of memory devices using a memory device address and control bus to read out data from the set of memory devices, and wherein the read data is provided to the second error correction logic.

17. The data processing system of claim 13, wherein if the second error correction logic is able to be corrected, then the second error correction logic generates pointers to correct data for bits of the read data that are determined to be incorrect.

18. The data processing system of claim 13, wherein, in response to receiving a write access request from the external memory controller, write data associated with the write access request is provided to first error correction code generation logic of the error correction logic of the memory hub controller, and wherein the first error correction code generation logic generates the first error correction codeword based on the write data and adds the first error correction codeword to the write data thereby forming modified write data.

19. The data processing system of claim 18, wherein the modified write data having the error correction bits is sent to the set of memory devices via the memory device data interface under control of the memory hub controller.

20. The data processing system of claim 13, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

21. The data processing system of claim 13, wherein the second error correction logic stores the read data in a read data queue along with a tag indicating the read data to be invalid if the second error correction logic determines that the read data contains an error that is not correctable by the second error correction logic.

22. The data processing system of claim 13, wherein the memory hub device further comprises second error correction code generation logic in the read logic integrated in the memory hub device, and wherein the second error correction code generation logic generates a second error correction codeword that is added to the read data before transmitting the read data to the external memory controller via the link interface responsive to the external memory controller expecting to receive the read data with an error correction codeword.