Semiconductor device and method for fabricating the same

• US 8,084,325 B2
• Filed: 06/30/2008
• Issued: 12/27/2011
• Est. Priority Date: 08/13/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Myung-Ok
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US12/165,129
• Publication Number:
  US 20090045465A1
• Time in Patent Office: 1,275 Days
• Field of Search: 438/259, 438/270, 257/366
• US Class Current: 438/259
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a recess pattern in a substrate;

forming a gate dielectric layer over the recess pattern;

forming a gate electrode over the gate dielectric layer inside the recess pattern, wherein the gate electrode does not extend above a surface of the substrate;

forming a gate hard mask pattern over the gate electrode and upper corners of the recess pattern;

forming a barrier layer over the gate hard mask pattern;

forming an interlayer dielectric layer over the barrier layer;

forming a contact hole by performing a self aligned contact (SAC) etching by using an etch selectivity between the interlayer dielectric layer and the barrier layer, wherein the substrate between the gate hard mask pattern and an adjacent gate hard mask pattern is recessed to a predetermined depth; and

forming a plug over the substrate between the gate hard mask pattern and the adjacent gate hard mask pattern by filling the contact hole.

2. The method of claim 1, wherein the gate hard mask pattern is formed over a portion of the substrate outside the recess pattern.

3. The method of claim 1, further comprising forming a gate spacer on lateral sides of the gate hard mask pattern.

4. The method of claim 1, wherein the gate electrode comprises a first gate conductive pattern and a second gate conductive pattern.

5. The method of claim 4, wherein forming the gate electrode comprises:

forming a first gate conductive layer to fill the recess pattern;

first etching the first gate conductive layer to form the first gate conductive pattern, wherein the first gate conductive layer is formed to a predetermined height inside the recess pattern;

forming a second gate conductive layer over the first gate conductive pattern to fill the recess pattern; and

second etching the second gate conductive layer to form the second gate conductive pattern inside the recess pattern.

6. The method of claim 4, wherein the first gate conductive pattern comprises a polysilicon layer, and the second gate conductive pattern comprises at least one layer selected from the group consisting of a tungsten (W) layer, a tungsten silicide (WSi_x, where x is a natural number) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, a tungsten nitride (WN) layer and a titanium nitride (TiN) layer.

7. The method of claim 5, wherein first etching comprises a dry etching.

8. The method of claim 5, wherein first etching comprises:

performing a first etch-back to remove the first gate conductive layer over the substrate outside the recess pattern; and

performing a second etch-back on the first gate conductive layer to form the first gate conductive pattern at the predetermined height inside the recess pattern.

9. The method of claim 8, wherein the first etch-back is performed at a process pressure of approximately 30 mTorr to approximately 100 mTorr, a maximum power of approximately 100 W to approximately 1,000 W, and a minimum power of approximately 50 W to approximately 800 W.

10. The method of claim 8, wherein the first etch-back is performed using an etching gas comprising a main gas selected from the group consisting of hydrogen bromide (HBr) gas, chlorine (Cl₂) gas and a combination thereof, and an additive gas selected from the group consisting of oxygen (O₂) gas, argon (Ar) gas, helium (He) gas and a combination thereof.

11. The method of claim 8, wherein the second etch-back is performed at a process pressure of approximately 30 mTorr to approximately 100 mTorr, a maximum power of approximately 100 W to approximately 1,000 W, and a minimum power of approximately 50 W to approximately 800 W.

12. The method of claim 8, wherein the second etch-back is performed using an etching gas comprising HBr gas, and an additive gas selected from the group consisting of O₂ gas, Ar gas, He gas and a combination thereof.

13. The method of claim 5, wherein second etching comprises wet etching.

14. The method of claim 13, wherein the wet etching is performed using a wet chemical comprising a sulfuric acid-peroxide mixture (SPM) or an ammonium hydroxide-peroxide mixture (APM).

15. The method of claim 1, wherein the gate hard mask pattern comprises at least one layer selected from the group consisting of a nitride layer, an amorphous carbon layer, a silicon oxynitride (SiON) layer, a tungsten (W) layer and a tungsten silicide (WSi_x, where x is a natural number) layer.

16. The method of claim 1, wherein the plug comprises a polysilicon layer.

17. The method of claim 1, wherein forming the gate hard mask pattern includes:

forming a gate hard mask layer over the substrate including the gate dielectric layer;

forming a photoresist pattern over the gate hard mask layer; and

etching the gate hard mask layer by using the photoresist pattern as an etch barrier.