Method for forming trench gate field effect transistor with recessed mesas using spacers

• US 8,084,327 B2
• Filed: 12/30/2008
• Issued: 12/27/2011
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sapp, Steven
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US12/346,626
• Publication Number:
  US 20090111227A1
• Time in Patent Office: 1,092 Days
• Field of Search: 438/270, 438/271, 438/272, 438/589, 438/259, 438/273, 257/E21.428
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions.

Claims

1. A method of forming a field effect transistor having an active area and a termination region surrounding the active area, comprising:

forming a well region in a first silicon region, the well region and the first silicon region being of opposite conductivity type;

forming gate trenches extending through the well region and terminating within the first silicon region;

forming a recessed gate in each gate trench;

forming a dielectric cap over each recessed gate;

removing a portion of the well region between adjacent trenches to expose upper sidewalls of each dielectric cap;

performing a blanket source implant to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches, the second silicon region being of the same conductivity type as first silicon region;

thereafter, forming a dielectric spacer along each exposed upper sidewall of the dielectric cap, every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region; and

recessing the second silicon region through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain, the remaining portions of the second silicon region forming source regions.

2. The method of claim 1 further comprising removing the dielectric spacers before forming the top-side conductor layer so that the top-side conductor layer contacts a top surface of each source region.

3. The method of claim 1 further comprising:

prior to forming the recessed gate, forming a thick bottom dielectric along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a gate dielectric lining the sidewalls of each gate trench, wherein the thick bottom dielectric is thicker than the gate dielectric.

4. The method of claim 1 further comprising:

prior to forming the recessed gate, forming a shield electrode along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a dielectric layer over each shield electrode.

5. The method of claim 1 further comprising:

forming a wide trench in the termination region; and

filling the wide trench with LOCOS.

6. The method of claim 1 further comprising forming a surface gate in the termination region simultaneously with forming the recessed gate in the gate trenches.

7. The method of claim 6 further comprising:

forming an opening over the surface gate; and

forming a gate conductor contacting the surface gate through the opening.

8. The method of claim 1 further comprising:

forming a termination trench in the termination region simultaneously with forming the gate trenches;

forming a recessed gate in the termination trench simultaneously with forming the recessed gate in the gate trenches;

forming an opening over the recessed gate in the termination trench; and

forming a gate conductor contacting the recessed gate in the termination trench through the opening.

9. A method of forming a field effect transistor having an active area and a termination region surrounding the active area, comprising:

forming a well region in a first silicon region, the well region and the first silicon region being of opposite conductivity type;

forming gate trenches extending through the well region and terminating within the first silicon region;

forming a recessed gate in each gate trench;

forming a dielectric cap over each recessed gate;

removing a portion of the well region between adjacent trenches to expose upper sidewalls of each dielectric cap;

thereafter, performing a blanket source implant to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches, the second silicon region being of the same conductivity type as first silicon region;

forming a dielectric spacer along each exposed upper sidewall of the dielectric cap, every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region; and

recessing the second silicon region through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain, the remaining portions of the second silicon region forming source regions.

10. The method of claim 9 further comprising removing the dielectric spacers before forming the top-side conductor layer so that the top-side conductor layer contacts a top surface of each source region.

11. The method of claim 9 further comprising:

prior to forming the recessed gate, forming a thick bottom dielectric along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a gate dielectric lining the sidewalls of each gate trench, wherein the thick bottom dielectric is thicker than the gate dielectric.

12. The method of claim 9 further comprising:

prior to forming the recessed gate, forming a shield electrode along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a dielectric layer over each shield electrode.

13. The method of claim 9 further comprising:

forming a wide trench in the termination region; and

filling the wide trench with LOCOS.

14. The method of claim 9 further comprising forming a surface gate in the termination region simultaneously with forming the recessed gate in the gate trenches.

15. The method of claim 14 further comprising:

forming an opening over the surface gate; and

forming a gate conductor contacting the surface gate through the opening.

16. The method of claim 9 further comprising:

forming a termination trench in the termination region simultaneously with forming the gate trenches;

forming a recessed gate in the termination trench simultaneously with forming the recessed gate in the gate trenches;

forming an opening over the recessed gate in the termination trench; and

forming a gate conductor contacting the recessed gate in the termination trench through the opening.