Methods of fabricating a semiconductor device
First Claim
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1. A method of fabricating a semiconductor device, the method comprising:
- forming a gate pattern on a substrate;
forming a capping pattern that covers an upper surface and sidewalls of the gate pattern, the capping pattern having a convex upper surface with respect to an upper surface of the substrate;
forming an interlayer insulation layer on the substrate such that an upper surface of the capping pattern is exposed;
removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized; and
forming an opening to expose the substrate adjacent to the capping pattern, after the removing the portion of the capping pattern and the interlayer insulation layer.
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Abstract
A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
57 Citations
20 Claims
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1. A method of fabricating a semiconductor device, the method comprising:
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forming a gate pattern on a substrate; forming a capping pattern that covers an upper surface and sidewalls of the gate pattern, the capping pattern having a convex upper surface with respect to an upper surface of the substrate; forming an interlayer insulation layer on the substrate such that an upper surface of the capping pattern is exposed; removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized; and forming an opening to expose the substrate adjacent to the capping pattern, after the removing the portion of the capping pattern and the interlayer insulation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of fabricating a semiconductor device, the method comprising:
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forming a transistor structure having a planar upper surface on a substrate; forming a capping pattern that covers an upper surface and sidewalls of the gate pattern, the capping pattern having a convex upper surface with respect to an upper surface of the substrate; removing a portion of the capping pattern and an interlayer insulating layer adjacent to the transistor structure; forming a cavity that exposes a portion of the substrate after the removing step; and forming a conductive plug in the cavity.
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20. A method of fabricating a semiconductor device, the method comprising:
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forming a gate pattern on a substrate; forming a capping pattern that covers an upper surface and sidewalls of the gate pattern, the capping pattern having a convex upper surface with respect to an upper surface of the substrate; forming an interlayer insulation layer on the substrate such that an upper surface of the capping pattern is exposed; and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
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Specification