Side stacking apparatus and method

• US 8,084,851 B2
• Filed: 02/23/2010
• Issued: 12/27/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Pham, Long
• Application Number:
  US12/710,811
• Publication Number:
  US 20100148343A1
• Time in Patent Office: 672 Days
• Field of Search: 257/686, 257/685, 257/E21.532, 257/E23.141, 438/109
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.

Claims

1. A module comprising:

a first integrated circuit (IC) electrically connected to a second IC by a physical connection located between facing surfaces of the first and second ICs, wherein the facing surfaces of the first and second ICs extend along a first plane; and

a third IC electrically connected to the physical connection, wherein the third IC includes a facing surface from which an electrically-conductive element extends, wherein the electrically-conductive element is electrically and physically connected to the physical connection, and wherein the facing surface of the third IC lies in a second plane that is substantially perpendicular to the first plane.

2. The module of claim 1, wherein the physical connection comprises a rigid post penetrated into a malleable material.

3. The module of claim 2, wherein the electrically-conductive element comprises a rigid post, and wherein the third IC is electrically connected to the physical connection by the electrically-conductive element which extends from the third IC into the malleable material.

4. The module of claim 3, wherein the third IC is located adjacent a first edge of the first IC and a first edge of the second IC that is offset from the first edge of the first IC such that the third IC is not exactly perpendicular to the first and second ICs, and wherein the length of the rigid post extending from the third IC is sufficient to compensate for the offset between the first edges of the first and second ICs.

5. The module of claim 1, wherein the physical connection comprises a confined solder connection, a fusion connection, a well-type connection, or a covalent bond connection.

6. The module of claim 1, wherein the third IC comprises a passive element electrically connecting at least one of the first or second ICs to a fourth IC.

7. The module of claim 6, wherein the passive element comprises a flexible portion.

8. The module of claim 7, wherein the passive element further comprises a rigid portion.

9. The module of claim 7, wherein the passive element wraps around at least two sides of at least one of the first or second ICs.

10. The module of claim 1, wherein the first IC comprises a first side surface and the second IC comprises a second side surface that is substantially aligned with the first side surface, and wherein the third IC comprises a facing surface that is substantially perpendicular to and adjacent to the first and second surfaces.

11. The module of claim 1, wherein the third IC is one IC in a stack of additional ICs.

12. The module of claim 1, further comprising a fourth IC electrically connected to the second IC and a fifth IC electrically connected to the fourth IC, wherein the third IC is substantially perpendicular to the fourth and fifth ICs, and wherein the third IC provides a bridge connection between the physical connection located between facing surfaces of the first and second ICs and another physical connection located between facing surfaces of the fourth and fifth ICs.

13. The module of claim 1, further comprising a spacer disposed between the first and second ICs, wherein the spacer is configured to establish a minimum allowable spacing between the first and second ICs.

14. The module of claim 13, wherein the spacer is part of one of the first or second ICs.

15. The module of claim 1, further comprising a contact disposed between the first and second ICs, wherein the contact is configured to establish a minimum allowable spacing between the first and second ICs.

16. A module comprising:

a stack of integrated circuits (ICs) including a first IC that is electrically connected to a second IC by a physical connection located between facing surfaces of the first and second ICs; and

a third IC including a facing surface from which an electrically-conductive element extends, wherein the facing surface of the third IC is positioned along a lateral surface of the stack, and wherein the third IC is electrically connected by the electrically-conductive element to at least one of the first or second ICs at the physical connection located between the facing surfaces of the first and second ICs.

17. The module of claim 16, wherein the third IC is substantially perpendicular to the first and second ICs.

18. The module of claim 16, wherein the physical connection comprises a rigid post extending into a malleable material.

19. The module of claim 16, wherein the physical connection comprises a confined solder connection, a fusion connection, a well-type connection, or a covalent bond connection.

20. The module of claim 16, wherein the third IC comprises a passive element electrically connecting at least one of the first or second ICs to a fourth IC.

21. The module of claim 20, wherein the passive element comprises a flexible portion and a rigid portion.

22. The module of claim 21, wherein the passive element wraps around at least two sides of the stack of ICs.

23. The module of claim 16, wherein the physical connection comprises a malleable material, and wherein the electrically-conductive element of the third IC extends into the malleable material.

24. The module of claim 16, wherein the lateral surface of the stack comprises a commonly-aligned edge that includes a first side surface of the first IC and a second side surface of the second IC, and wherein the third IC comprises a facing surface that is substantially perpendicular to the commonly-aligned edge.

25. The module of claim 16, wherein the stack of ICs further comprises a fourth IC electrically connected to the second IC and a fifth IC electrically connected to the fourth IC, and wherein the third IC provides a bridge connection between the physical connection located between the first and second ICs and a physical connection located between the fourth and fifth ICs.

26. The module of claim 16, further comprising a spacer disposed between the first and second ICs, wherein the spacer is configured to establish a minimum spacing between the first and second ICs.

27. The module of claim 16, wherein the first and second ICs are misaligned such that a first side surface of the first IC is not commonly-aligned with a second side surface of the second IC, and wherein the first and second side surfaces correspond to the lateral surface of the stack of ICs.

28. A module comprising:

a first integrated circuit (IC) electrically and physically coupled to both a second IC and a third IC at a common connection point, wherein the first IC includes a first element extending from a first facing surface, wherein the second IC includes a second element extending from a second facing surface, wherein the third IC includes a third element extending from a third facing surface, wherein the first, second, and third elements are electrically and physically connected at the common connection point, and wherein the third facing surface lies in a plane that is substantially perpendicular to a plane in which the first and second facing surfaces lie.

29. The module of claim 28, wherein the first and second ICs are arranged in a facing relationship and the common connection point is between the first and second ICs.

30. The module of claim 28, wherein the third IC is positioned adjacent lateral edges of the first and second ICs.

31. The module of claim 30, wherein the lateral edges of the first and second ICs are not coplanar and the third IC is arranged at an angle other than 90 degrees with respect to the first and second ICs.

32. The module of claim 28, wherein the common connection point comprises a malleable material and the first and third ICs each include at least one rigid post that penetrates into the malleable material.

33. The module of claim 28, wherein the common connection point comprises a confined solder connection, a fusion connection, a well-type connection, or a covalent bond connection.

34. The module of claim 28, wherein the third IC comprises a passive element electrically connecting at least one of the first or second ICs to a fourth IC.

35. A method comprising:

electrically connecting a first integrated circuit (IC) to a second IC via a physical connection located between facing surfaces of the first and second ICs, wherein the facing surfaces of the first and second ICs extend along a first plane; and

electrically connecting a third IC to the physical connection, wherein the third IC includes a facing surface from which an electrically-conductive element extends, wherein the electrically-conductive element is electrically and physically connected to the physical connection, and wherein the facing surface of the third IC lies in a second plane that is substantially perpendicular to the first plane.

36. The method of claim 35, wherein said electrically connecting a third IC to the physical connection comprises inserting the electrically-conductive element into a malleable material.

37. The method of claim 36, wherein the electrically-conductive element comprises a rigid post, and wherein the physical connection between facing surfaces of the first and second ICs comprises the malleable material.

38. The method of claim 35, wherein said electrically connecting a third IC to the physical connection comprises one of a fusion process or a covalent bonding process.

39. The method of claim 35, wherein said electrically connecting a third IC to the physical connection comprises a solder reflow process, and wherein reflowed solder is confined to a well.

40. The method of claim 35, wherein said electrically connecting a third IC to the physical connection comprises electrically connecting at least one of the first or second ICs to a passive element of the third IC, the method further comprising electrically connecting the passive element to a fourth IC such that an electrical connection is formed between the fourth IC and at least one of the first or second ICs.

41. The method of claim 40, wherein the passive element comprises a flexible portion and a rigid portion.

42. The method of claim 35, wherein the first IC comprises a first side surface and the second IC comprises a second side surface that is substantially aligned with the first side surface, the method further comprising positioning the facing surface of the third IC substantially perpendicular to and adjacent to the first and second side surfaces.

43. The method of claim 35, further comprising:

electrically connecting a fourth IC to the second IC;

electrically connecting a fifth IC to the fourth IC; and

providing an electrical bridge connection between the physical connection located between facing surfaces of the first and second ICs and another physical connection located between facing surfaces of the fourth and fifth ICs.

44. The method of claim 35, further comprising providing a spacer between the first and second ICs, wherein the spacer is configured to establish a minimum allowable spacing between the first and second ICs.

45. The method of claim 44, wherein the spacer is part of one of the first or second ICs.

46. The method of claim 35, wherein a first side surface of the first IC is not commonly-aligned with a second side surface of the second IC such that the third IC is arranged at an angle other than 90 degrees with respect to the first and second ICs.

47. A method comprising:

electrically connecting a first integrated circuit (IC) to a second integrated circuit by a physical connection located between facing surfaces of the first and second ICs to form a stack of ICs;

positioning a third IC on a lateral surface of the stack of ICs, wherein the third IC includes a facing surface from which an electrically-conductive element extends; and

electrically connecting, via the electrically-conductive element, the third IC to at least one of the first or second ICs at the physical connection located between the facing surfaces of the first and second ICs.

48. The method of claim 47, wherein said electrically connecting the third IC to at least one of the first or second ICs comprises inserting the electrically-conductive element of the third IC into a malleable material of the physical connection.

49. The method of claim 47, wherein said electrically connecting the third IC to at least one of the first or second ICs comprises one of a fusion process, a covalent bonding process, or a solder reflow process.

50. The method of claim 47, wherein the stack of ICs comprises a commonly-aligned edge that includes a first side surface of the first IC and a second side surface of the second IC, the method further comprising positioning the facing surface of the third IC substantially perpendicular to and adjacent to the commonly-aligned edge.

51. The method of claim 47, further comprising:

electrically connecting a fourth IC to the second IC;

electrically connecting a fifth IC to the fourth IC, wherein the stack of ICs includes the fourth and fifth ICs; and

providing an electrical, bridge connection between the connection point located between the facing surfaces of the first and second ICs and another connection point located between facing surfaces of the fourth and fifth ICs.