Semiconductor package with fast power-up cycle and method of making same

• US 8,084,868 B1
• Filed: 06/18/2010
• Issued: 12/27/2011
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: St. Amand, Roger D., Perelman, Vladimir
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US12/818,446
• Time in Patent Office: 557 Days
• Field of Search: 257/777, 257/724, 257/783, 257/787, 257/E23.169
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/83136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including at least two electronic components which are provided in a stacked arrangement, and are each electrically connected to an underlying substrate through the use of conductive wires. In accordance with one embodiment of the present invention, the electronic components are separated from each other by an intervening spacer which is typically fabricated from aluminum, or from silicon coated with aluminum. In this particular embodiment, the uppermost electronic component of the stack is electrically connected to at least one of the conductive wires through the use of a conductive paste layer which is also used to secure the uppermost electronic component to the underlying spacer. In this regard, one end of one of the conductive wires may be embedded in the conductive paste layer adjacent one side of the uppermost electronic component, or between the bottom surface of such electronic component and the spacer.

Claims

1. A semiconductor package, comprising:

a substrate;

a first electronic component attached and electrically connected to the substrate;

a spacer attached to the first electronic component;

a second electronic component defining a peripheral side surface, the second electronic component being attached to the spacer by a conductive paste layer and electrically connected to the substrate by at least one conductive wire which is partially encapsulated by the conductive paste layer, the conductive wire having a first end which is attached to the spacer at a location disposed outward relative to the side surface of the second electronic component, and an opposed second end which is electrically connected to the substrate.

2. The semiconductor package of claim 1 wherein the first electronic component is electrically connected to the substrate by a conductive wire.

3. The semiconductor package of claim 1 wherein the second electronic component is also electrically connected to the substrate by another conductive wire.

4. The semiconductor package of claim 1 wherein the substrate comprises:

an insulative layer defining opposed first and second surfaces;

a plurality of lands disposed on the first surface; and

a conductive pattern disposed on the second surface and electrically connected to the lands in a prescribed manner, the first and second electronic components each being electrically connected to the conductive pattern.

5. The semiconductor package of claim 1 wherein the first end of the conductive wire which is partially encapsulated by the conductive paste layer is attached to the spacer via a stitch-bond.

6. A semiconductor package, comprising:

a substrate;

a first electronic component attached to the substrate;

a spacer attached to the first electronic component, the spacer comprising a core which is at least partially covered by an outer conductive layer;

a second electronic component defining a peripheral side surface, the second electronic component being attached to the outer conductive layer of the spacer by a conductive paste layer; and

a conductive wire which is partially encapsulated by the conductive paste layer, the conductive wire having a first end that is attached to the outer conductive layer of the spacer at a location which is disposed outward relative to the side surface of the second electronic component.

7. The semiconductor package of claim 6 wherein the substrate comprises:

an insulative layer defining opposed first and second surfaces;

a plurality of lands disposed on the first surface; and

a conductive pattern disposed on the second surface and electrically connected to the lands in a prescribed manner, the conductive wire being electrically connected to the conductive pattern.

8. The semiconductor package of claim 6 further comprising a package body which at least partially encapsulates the first and second electronic components, the spacer, the conductive wire, and the substrate.

9. The semiconductor package of claim 8 wherein the conductive wire which is partially encapsulated by the conductive paste layer is also partially covered by the package body.

10. The semiconductor package of claim 6 wherein the first end of the conductive wire is attached to the outer conductive layer of the spacer via a stitch-bond.

11. A semiconductor package, comprising:

a substrate;

a first electronic component attached and electrically connected to the substrate;

a spacer attached to the first electronic component;

a second electronic component attached to the spacer by a conductive paste layer and electrically connected to the conductive pattern of the substrate by at least one conductive wire which is partially encapsulated by the conductive paste layer, the conductive wire having a first end which is attached to a prescribed location on the spacer and an opposed second end which is electrically connected to the substrate, the second electronic component comprising a transistor having a collector which is electrically connected to the conductive wire by the conductive paste layer, and an emitter which is electrically connected to the substrate by another conductive wire.

12. A semiconductor package, comprising:

a substrate;

a first electronic component attached to the substrate;

a spacer attached to the first electronic component, the spacer comprising a core which is at least partially covered by an outer conductive layer;

a second electronic component attached to the outer conductive layer of the spacer by a conductive paste layer; and

a conductive wire which is partially encapsulated by the conductive paste layer;

the second electronic component comprising a transistor having an emitter which is electrically connected to the substrate and a collector which is electrically connected to the conductive wire by the conductive paste layer.