Logic module including versatile adder for FPGA

• US 8,085,064 B2
• Filed: 06/25/2010
• Issued: 12/27/2011
• Est. Priority Date: 04/11/2007
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Feng, Wenyi, Greene, Jonathan
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US12/823,266
• Publication Number:
  US 20100271068A1
• Time in Patent Office: 550 Days
• Field of Search: 326 37- 1, 326/47, 327/108, 327/109
• US Class Current: 326/38
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.

Claims

1. A logic module including:

N data inputs;

a carry input;

a logic output;

a sum output;

a carry output;

a group of 2^N configuration memory cells, each configuration memory cell having an output;

an N-input LUT formed from an N-level tree of 2;

1 multiplexers, each multiplexer in a level of the tree having multiplexer select inputs coupled together to a unique one of the N data inputs and having first and second multiplexer data inputs and a multiplexer output, the first and second multiplexer data inputs in each level of the tree being connected in a tree structure to multiplexer outputs of the next higher level of the tree, the first and second multiplexer data inputs of each of the multiplexers in the Nth level of the tree being connected to the output of a different one of the configuration memory cells, and the output of the multiplexer in the first level of the tree being coupled to the logic output;

a tapping multiplexer having at least two data inputs, at least one select input and an output, the data inputs each being coupled to a unique member of the subset of the multiplexer outputs internal to the N-input LUT, two of the at least two data inputs being coupled to multiplexer outputs in different levels of the tree, and the select inputs being coupled to a source of configuration data;

a carry multiplexer having a first data input coupled to the carry input, a second data input coupled to the output of the tapping multiplexer, a select input coupled to the logic output and an output coupled to the carry output; and

an XOR gate having a first input coupled to the logic output, a second input coupled to the carry input, and an output coupled to the sum output.

2. The logic module of claim 1 wherein N data inputs comprises 4 data inputs.

3. The logic module of claim 1 wherein the tapping multiplexer has three data inputs, each data input coupled to an output of a multiplexer in a different level of the tree.

4. A logic module including:

N data inputs;

a carry input;

a G input;

a logic/sum output;

a carry output;

a group of 2^N configuration memory cells, each configuration memory cell having an output;

an N-input LUT formed from an N-level tree of 2;

1 multiplexers, each multiplexer in a level of the tree having multiplexer select inputs coupled together to a unique one of the N data inputs and having first and second multiplexer data inputs and a multiplexer output, the first and second multiplexer data inputs in each level of the tree being connected in a tree structure to multiplexer outputs of the next higher level of the tree, the first and second multiplexer data inputs of each of the multiplexers in the Nth level of the tree being connected to the output of a different one of the configuration memory cells, and the output of the multiplexer in the first level of the tree being coupled to the logic/sum output;

a carry multiplexer having a first data input coupled to the carry input, a second data input coupled to the G input, a select input coupled to the logic output, and an output coupled to the carry output; and

a carry-in multiplexer having a first data input coupled to the carry input, a at least one other data input, at least one select input coupled to at least one carry-in multiplexer memory cell, the logic output, and an output coupled to a select input of the multiplexer in the first level of the tree.

5. The logic module of claim 4 wherein N data inputs comprises 4 data inputs.

6. A logic module including:

N data inputs;

a carry input;

a logic output;

a sum output;

a carry output;

a group of 2^N configuration memory cells, each configuration memory cell having an output;

an N-input LUT formed from an N-level tree of 2;

1 multiplexers, each multiplexer in a level of the tree having multiplexer select inputs coupled together to a unique one of the N data inputs and having first and second multiplexer data inputs and a multiplexer output, the first and second multiplexer data inputs in each level of the tree being connected in a tree structure to multiplexer outputs of the next higher level of the tree, the first and second multiplexer data inputs of each of the multiplexers in the Nth level of the tree being connected to the output of a different one of the configuration memory cells, and the output of the multiplexer in the first level of the tree being coupled to the logic output;

a tapping multiplexer having at least three data inputs, a plurality of select inputs being coupled to a source of configuration data, a first data input being coupled to the output of a first multiplexer in the second level of the tree, a second data input being coupled to the output of a second multiplexer in the second level of the tree, a third input coupled to a first constant logic level, and an output;

a carry multiplexer having a first data input coupled to the carry input, a second data input coupled to the output of the tapping multiplexer, a select input, and an output coupled to the carry output;

a carry-multiplexer-select multiplexer having a first data input coupled to the logic output, a second data input coupled to the first constant logic level, a select input coupled to a source of configuration data, and an output coupled to the select input of the carry multiplexer; and

an XOR gate having a first input coupled to the logic output, a second input coupled to the carry input, and an output coupled to the sum output.

7. The logic module of claim 6, wherein the tapping multiplexer further includes a fourth data input coupled to a second constant logic level opposite to the first constant logic level.

8. The logic module of claim 6 wherein N data inputs comprises 4 data inputs.