PLL circuit

• US 8,085,098 B2
• Filed: 09/15/2009
• Issued: 12/27/2011
• Est. Priority Date: 10/10/2008
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Yamazaki, Yoshikazu
• Primary Examiner(s): Chang, Joseph
• Assistant Examiner(s): SHIN, JEFFREY M
• Application Number:
  US12/560,395
• Publication Number:
  US 20100090768A1
• Time in Patent Office: 833 Days
• Field of Search: 331/10, 331/11, 331/15, 331/16, 331/57, 331/182, 331/183, 331/185, 331/186
• US Class Current: 331/10
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A PLL circuit comprising an oscillation unit, a frequency division unit, a phase comparison unit, and a generation unit comprises a switching unit that switches between a first state in which a control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and a correction unit that, in the second state, compares the control voltage output from the generation unit with the reference voltage, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the control voltage output from the generation unit is equivalent to the reference voltage.

Claims

1. A PLL circuit comprising:

an oscillation unit that generates an internal signal by oscillating at a frequency according to an input voltage;

a frequency division unit that divides a frequency of the internal signal so as to generate a frequency-divided signal;

a phase comparison unit that compares a phase of a reference signal input from outside with a phase of the frequency-divided signal received from the frequency division unit, and outputs a phase error signal according to a result of the comparison;

a generation unit that generates a control voltage based on the phase error signal;

a switching unit that switches between a first state in which the control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and

a correction unit that, in the second state, compares the control voltage output from the generation unit with the reference voltage, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the control voltage output from the generation unit is equivalent to the reference voltage, wherein the correction unit corrects a gain of the oscillation unit such that the control voltage output from the generation unit is equivalent to the reference voltage, the gain being a property of the frequency at which the oscillation unit oscillates with respect to the voltage input into the oscillation unit,

wherein the oscillation unit comprises;

an input transistor comprising a gate into which the control voltage or the reference voltage is input;

a current mirror circuit that supplies a current according to a current that flows between a source and a drain of the input transistor; and

a ring oscillator that receives the current supplied by the current mirror circuit, and oscillates at a frequency according to a magnitude of the received current, and

wherein the correction unit comprises;

a MOS transistor whose mutual conductance is controlled based on a result of the comparison of the control voltage received from the generation unit, and the reference voltage, wherein the mutual conductance of the MOS transistor decreases when the control voltage is higher than the reference voltage, and the mutual conductance of the MOS transistor increases when the control voltage is lower than the reference voltage;

a voltage comparison unit that compares the control voltage received from the generation unit with the reference voltage, and outputs a voltage error signal according to a result of the comparison;

a holding unit that temporarily holds the voltage error signal output from the voltage comparison unit;

a control value holding unit that changes a held digital control value according to the voltage error signal output from the holding unit, and holds the changed digital control value; and

a D/A conversion unit that generates an analog control value by performing D/A conversion of the changed digital control value that was output from the control value holding unit,

wherein the MOS transistor comprises a gate into which the analog control value output from the D/A conversion unit is input, a source connected to a ground voltage, and a drain connected to the source of the input transistor.

2. The PLL circuit according to claim 1,

wherein the control value holding unit increments a held digital control value and holds the digital control value that has been incremented when the voltage error signal indicates that the control voltage is higher than the reference voltage, and decrements the held digital control value and holds the digital control value that has been decremented when the voltage error signal indicates that the control voltage is lower than the reference voltage,

the MOS transistor increases the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been incremented is input into the gate, and reduces the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been decremented is input into the gate, and

the gain of the oscillation unit rises when the magnitude of the current that flows between the source and the drain of the input transistor increases, and lowers when the magnitude of the current that flows between the source and the drain of the input transistor decreases.

3. A PLL circuit comprising:

an oscillation unit that generates an internal signal by oscillating at a frequency according to an input voltage;

a frequency division unit that divides a frequency of the internal signal so as to generate a frequency-divided signal;

a phase comparison unit that compares a phase of a reference signal input from outside with a phase of the frequency-divided signal received from the frequency division unit, and outputs a phase error signal according to a result of the comparison;

a generation unit that generates a control voltage based on the phase error signal;

a switching unit that switches between a first state in which the control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and

a correction unit that, in the second state, compares the control voltage output from the generation unit with the reference voltage, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the control voltage output from the generation unit is equivalent to the reference voltage, wherein the correction unit corrects a gain of the oscillation unit such that the control voltage output from the generation unit is equivalent to the reference voltage, the gain being a property of the frequency at which the oscillation unit oscillates with respect to the voltage input into the oscillation unit,

wherein the oscillation unit comprises;

an input transistor including a gate into which the control voltage or the reference voltage is input;

a current mirror circuit that supplies a current according to a current that flows between a source and a drain of the input transistor; and

a ring oscillator that receives the current supplied by the current mirror circuit, and oscillates at a frequency according to a magnitude of the received current, and

wherein the correction unit comprises;

a MOS transistor whose mutual conductance is controlled based on a result of the comparison of the control voltage received from the generation unit, and the reference voltage, wherein the mutual conductance of the MOS transistor decreases when the control voltage is higher than the reference voltage, and the mutual conductance of the MOS transistor increases when the control voltage is lower than the reference voltage;

a differential amplifier that generates and outputs a differential signal between the control voltage received from the generation unit and the reference voltage;

a holding unit that temporarily holds a differential voltage according to the differential signal output from the differential amplifier;

an A/D conversion unit that performs A/D conversion of the differential voltage held by the holding unit so as to generate a digital control value;

a D/A conversion unit that performs D/A conversion of the digital control value so as to generate an analog control value;

wherein the MOS transistor comprises a gate into which the analog control value output from the D/A conversion unit is input, a source connected to a ground voltage, and a drain connected to the source of the input transistor.

4. The PLL circuit according to claim 3,

wherein the differential amplifier increases the differential voltage held by the holding unit and causes the holding unit to hold the increased differential voltage when outputting the differential signal indicating that the control voltage is higher than the reference voltage, and reduces the differential voltage held by the holding unit and causes the holding unit to hold the reduced differential voltage when outputting the differential signal indicating that the control voltage is lower than the reference voltage,

the MOS transistor increases the magnitude of a current that flows between the source and the drain of the input transistor when an analog control value corresponding to the increased differential voltage is input into the gate, and reduces the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the reduced differential voltage is input into the gate, and

the gain of the oscillation unit rises when the magnitude of the current that flows between the source and the drain of the input transistor increases, and lowers when the magnitude of the current that flows between the source and the drain of the input transistor decreases.

5. A PLL circuit comprising:

an oscillation unit that generates an internal signal by oscillating at a frequency according to an input voltage;

a frequency division unit that divides a frequency of the internal signal so as to generate a frequency-divided signal;

a phase comparison unit that compares a phase of a reference signal input from outside with a phase of the frequency-divided signal received from the frequency division unit, and outputs a phase error signal according to a result of the comparison;

a generation unit that generates a control voltage based on the phase error signal;

a switching unit that switches between a first state in which the control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and

a correction unit that, in the second state, compares a frequency of the frequency-divided signal with a frequency of the reference signal, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the frequency of the frequency-divided signal is equivalent to the frequency of the reference signal, wherein the correction unit corrects a gain of the oscillation unit such that the frequency of the frequency-divided signal is equivalent to the frequency of the reference signal, the gain being a property of the frequency at which the oscillation unit oscillates with respect to the voltage input into the oscillation unit,

wherein the oscillation unit comprises;

an input transistor comprising a gate into which the control voltage or the reference voltage is input;

a current mirror circuit that supplies a current according to a current that flows between a source and a drain of the input transistor; and

a ring oscillator that receives the current supplied by the current mirror circuit, and oscillates at a frequency according to a magnitude of the received current, and

wherein the correction unit comprises;

a MOS transistor whose mutual conductance is controlled based on a result of the comparison of the frequency of the reference signal and the frequency of the frequency-divided signal, wherein the mutual conductance of the MOS transistor decreases when the frequency of the frequency-divided signal is higher than the frequency of the reference signal, and the mutual conductance of the MOS transistor increases when the frequency of the frequency-divided signal is lower than the frequency of the reference signal;

a frequency comparison unit that compares the frequency of the frequency-divided signal received from the frequency division unit with the frequency of the reference signal received from the outside, and outputs a difference signal according to a result of the comparison;

a control value holding unit that changes a held digital control value according to the difference signal output from the frequency comparison unit, and holds the changed digital control value;

a D/A conversion unit that generates an analog control value by performing D/A conversion of the changed digital control value that was output from the control value holding unit;

wherein the MOS transistor comprises a gate into which the analog control value output from the D/A conversion unit is input, a source connected to a reference voltage, and a drain connected to the source of the input transistor.

6. The PLL circuit according to claim 5, wherein the frequency comparison unit comprises:

a first counter that calculates the frequency of the frequency-divided signal by counting a number of clocks of the frequency-divided signal received from the frequency division unit;

a second counter that calculates the frequency of the reference signal by counting a number of clocks of the reference signal received from the outside; and

a subtractor that generates and outputs a difference signal by subtracting a value counted by the first counter from a value counted by the second counter.

7. The PLL circuit according to claim 5,

wherein the control value holding unit increments the held digital control value and holds the digital control value that has been incremented when the difference signal indicates that the frequency of the frequency-divided signal is lower than the frequency of the reference signal, and decrements the held digital control value and holds the digital control value that has been decremented when the difference signal indicates that the frequency of the frequency-divided signal is higher than the frequency of the reference signal,

the MOS transistor increases the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been incremented is input into the gate, and reduces the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been decremented is input into the gate, and

the gain of the oscillation unit rises when the magnitude of the current that flows between the source and the drain of the input transistor increases, and lowers when the magnitude of the current that flows between the source and the drain of the input transistor decreases.

8. A PLL circuit comprising:

an oscillation unit that generates an internal signal by oscillating at a frequency according to an input voltage;

a frequency division unit that divides a frequency of the internal signal so as to generate a frequency-divided signal;

a phase comparison unit that compares a phase of a reference signal input from outside with a phase of the frequency-divided signal received from the frequency division unit, and outputs a phase error signal according to a result of the comparison;

a generation unit that generates a control voltage based on the phase error signal;

a switching unit that switches between a first state in which the control voltage output from the generation unit is input into the oscillation unit, a third state in which a first reference voltage is input into the oscillation unit, and a fourth state in which a second reference voltage higher than the first reference voltage is input into the oscillation unit; and

a correction unit that compares an absolute value of frequency difference between a frequency of the frequency-divided signal in the third state and a frequency of the frequency-divided signal in the fourth state with a desired value, and that corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the absolute value of the frequency difference between the frequency of the frequency-divided signal in the third state and the frequency of the frequency-divided signal in the fourth state is equivalent to the desired value.

9. The PLL circuit according to claim 8,

wherein the correction unit corrects a gain of the oscillation unit such that the absolute value of the frequency difference between the frequency of the frequency-divided signal in the third state and the frequency of the frequency-divided signal in the fourth state is equivalent to the desired value, the gain being a property of the frequency at which the oscillation unit oscillates with respect to the voltage input into the oscillation unit.

10. The PLL circuit according to claim 9,

wherein the correction unit corrects the gain of the oscillation unit such that the gain of the oscillation unit rises when the absolute value of the frequency difference is lower than the desired value, and such that the gain of the oscillation unit lowers when the absolute value of the frequency difference is higher than the desired value.

11. The PLL circuit according to claim 9, wherein the oscillation unit comprises:

an input transistor comprising a gate into which the control voltage or the reference voltage is input;

a current mirror circuit that supplies a current according to a current that flows between a source and a drain of the input transistor; and

a ring oscillator that receives the current supplied by the current mirror circuit, and oscillates at a frequency according to a magnitude of the received current.

12. The PLL circuit according to claim 11,

wherein the correction unit comprises a MOS transistor whose mutual conductance is controlled based on a result of the comparison of the frequency of the reference signal and the frequency of the frequency-divided signal,

the mutual conductance of the MOS transistor decreases when the frequency of the frequency-divided signal is higher than the frequency of the reference signal, and

the mutual conductance of the MOS transistor increases when the frequency of the frequency-divided signal is lower than the frequency of the reference signal.

13. The PLL circuit according to claim 12, wherein the correction unit comprises:

a frequency difference comparison unit that compares the absolute value of the frequency difference with the desired value, and outputs a difference signal according to a result of the comparison;

a control value holding unit that changes a held digital control value according to the difference signal output from the frequency difference comparison unit, and holds the changed digital control value;

a D/A conversion unit that generates an analog control value by performing D/A conversion of the changed digital control value that was output from the control value holding unit;

wherein the MOS transistor comprises a gate into which the analog control value output from the D/A conversion unit is input, a source connected to a reference voltage, and a drain connected to the source of the input transistor.

14. The PLL circuit according to claim 13, wherein the frequency difference comparison unit comprises:

a third counter that calculates the frequency of the frequency-divided signal in the third state by counting a number of clocks of the frequency-divided signal in the third state;

a fourth counter that calculates the frequency of the frequency-divided signal in the fourth state by counting a number of clocks of the frequency-divided signal in the fourth state; and

a subtractor that generates and outputs the difference signal by subtracting a value counted by the third counter from a value counted by the fourth counter, and further subtracting the desired value from a result obtained through the subtraction.

15. The PLL circuit according to claim 13,

wherein the control value holding unit increments the held digital control value and holds the digital control value that has been incremented when the difference signal indicates that the absolute value of the frequency difference is smaller than the desired value, and decrements the held digital control value and holds a digital control value that has been decremented when the difference signal indicates that the absolute value of the frequency difference is larger than the desired value,

the MOS transistor increases the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been incremented is input into the gate, and reduces the magnitude of the current that flows between the source and the drain of the input transistor when an analog control value corresponding to the digital control value that has been decremented is input into the gate, and

the gain of the oscillation unit rises when the magnitude of the current that flows between the source and the drain of the input transistor increases, and lowers when the magnitude of the current that flows between the source and the drain of the input transistor decreases.