Digital-compatible multi-state-sense input

• US 8,085,857 B1
• Filed: 09/22/2004
• Issued: 12/27/2011
• Est. Priority Date: 09/25/2003
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Baumbach, Jason
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): NEFF, MICHAEL R
• Application Number:
  US10/947,890
• Time in Patent Office: 2,652 Days
• Field of Search: 375/257, 371/21
• US Class Current: 375/257
• CPC Class Codes: H04B 3/00 Line transmission systems combined with near-field transmission systems H04B5/00
• CPC Class Codes: H04L 25/029 Provision of high-impedance states
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20

Abstract

A method and an apparatus are described for sensing of a multi-state signal. An embodiment of a method includes driving a digital input line with a signal, the signal alternating between a first state and a second state. The method further includes sensing one or more values of the digital input line, and determining a state of the digital input line based on the sensed values.

Claims

1. A method comprising:

driving a digital input line with a signal, the driven signal alternating between a first state and a second state in accordance with a clock cycle;

sensing one or more values of the digital input line;

determining a state of the digital input line based on the sensed values, wherein determining the state of the digital input line comprises determining that the digital input line is in a third state if the sensed value of the digital input line matches the state of the alternating driven signal for a plurality of clock cycles of the alternating driven signal; and

incrementing a counter, wherein the counter is incremented when the sensed value of the digital input line matches the state of the alternating driven signal for the plurality of clock cycles and determining the state of the digital input line comprises determining that the digital input line is in the third state if the counter reaches a specified value.

2. The method of claim 1, wherein the first state represents a high state and the second state represents a low state.

3. The method of claim 1, wherein determining the state of the digital input line comprises determining that the digital input line is in the first state if the alternating driven signal is in the second state and the sensed value is the first state.

4. The method of claim 3, wherein determining the state of the digital input line further comprises determining that the digital input line is in the second state if the alternating driven signal is in the first state and the sensed value is the second state.

5. The method of claim 1, wherein the third state represents a high impedance state.

6. The method of claim 1, further comprising waiting a delay period between the driving of the signal and the sensing of the one or more values of the digital input line.

7. An apparatus comprising:

a sensing circuit to sense a digital state for an input line, wherein the input line receives a signal that is one of a high state, a low state, or a non-driven state;

a driver to drive a signal on the input line, the driven signal alternating between a high signal and a low signal in accordance with a clock cycle, wherein the input line is deemed to have received a non-driven signal if a state detected on the input line matches the state of the alternating signal driven on the input line by the driver for a plurality of clock cycles of the alternating driven signal; and

incrementing a counter, wherein the counter is incremented when the state detected on the input line matches the state of the alternating signal driven on the input line by the driver for the plurality of clock cycles and the input line is deemed to have received the non-driven signal when the counter reaches a specified value.

8. The apparatus of claim 7, wherein the driver comprises a flip-flop device.

9. The apparatus of claim 7, wherein the driver provides a weaker signal than a normal signal for the input line.

10. The apparatus of claim 7, wherein the input line is deemed to have received a high signal if a high state is detected on the input line after a low signal is driven on the input line by the driver, and wherein the input line is deemed to have received a low signal if a low state is detected after a high signal is driven on the input line by the driver.

11. A sensing device comprising:

a component to sense a state for a digital input;

a driver coupled with the component, the driver to drive a weak signal on the digital input, wherein the weak signal alternates between a high signal and a low signal in accordance with a clock cycle;

a state machine coupled with the component, the state machine to decode a signal on the digital input to one of a plurality of conditions based on the sensed state, wherein the plurality of conditions comprise a low state, a high state, and a high-impedance state, and wherein the state machine decodes the high impedance state if the sensed signal matches the alternating driven signal by the driver for a plurality of clock cycles of the alternating driven signal; and

a counter, wherein the counter is incremented when the sensed signal matches the alternating driven signal by the driver for the plurality of clock cycles and the state machine decodes the high impedance state when the counter reaches a specified value.

12. The sensing device of claim 11, wherein the state machine decodes the high state if the component senses a high signal and the driver drives a low signal.

13. The sensing device of claim 11, wherein the state machine decodes the low state if the component senses a low signal and the driver drives a high signal.