Methods for managing alignment and latency in interference cancellation

• US 8,085,889 B1
• Filed: 09/19/2007
• Issued: 12/27/2011
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC
• Original Assignee: Rambus Inc.
• Inventors: Jain, Prashant, Narayan, Anand P, Graham, Greg, Meyer, David R
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US11/858,074
• Time in Patent Office: 1,560 Days
• Field of Search: 375/346, 375/347
• US Class Current: 375/346
• CPC Class Codes: G01S 19/22 Multipath-related issues
• CPC Class Codes: G01S 5/10 Position of receiver fixed by co-ordinating a plurality of position lines defined by path-difference measurements , e.g. omega or decca systemsG01S5/12 takes precedence ; beacons and receivers cooperating therewith G01S1/306, G01S1/308
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7105 Joint detection techniques, e.g. linear detectors
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 2001/70935 using a bank of matched fileters, e.g. Fast Hadamard Transform
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.

Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Claims

1. An interference cancelling receiver, comprising

at least one symbol estimator operates on a signal stream to produce a plurality of symbol estimates from a signal stream;

a plurality of interference estimators that is coupled to the said at least one symbol estimator to produce a plurality of interference estimates; and

an interference estimate combiner coupled to the said plurality of interference estimators where the plurality of interference estimates are aligned to a received time boundary to produce a composite interference estimate;

wherein the symbol estimator operates sequentially on a sorted list of sources, sorted on the basis of their earliest arriving multipath.

2. A method for performing interference cancellation comprising:

providing for computing symbol estimates from a combined data stream;

providing for post-processing the symbol estimates using at least one of a means for thresholding or means for weighting to produce modified symbol estimates;

providing for using said modified symbol estimates to created a plurality of interference estimates;

providing for realigning at least one of the plurality interference estimates away from its symbol boundary and aligning to an arbitrary reference time;

providing for combining a plurality of interference estimates aligned to the arbitrary reference time to create a combined interference estimate; and

providing for using the combined interference estimate to create at least one interference cancelled signal stream.

3. The method recited in claim 2, further comprising:

providing for aligning chip-level data from a plurality of paths from a single source to the symbol boundary of each of said plurality of paths to produce a plurality of aligned paths; and

providing for combining the plurality of aligned paths to produce a combined data stream.

4. The method recited in claim 2, where providing for combining a plurality of interference estimates comprises providing for summing to combine a plurality of interference estimates.

5. The method recited in claim 2, where the combined data stream comprises interference cancelled data.

6. The method recited in claim 2, where the combined data stream comprises a combination of interference cancelled data and raw signal.

7. A chipset that performs interference cancellation comprising:

a front-end for receiving a signal;

a combiner coupled to the front-end that produces a single data stream per source;

a symbol estimator coupled to the combiner for generating symbol estimates;

an interference estimator operating on the symbol estimates to generate a plurality of interference estimates; and

an interference removal module for producing at least one segment of an interference cancelled signal from the plurality of interference estimates;

wherein at least two consecutive segments of said interference estimates are used to produce said one segment of an interference cancelled signal.

8. The chipset recited in claim 7, where said one segment comprises an integer multiple of a symbol length.

9. The chipset recited in claim 7, where the symbol estimator comprises a Fast Hadamard Transform module.

10. The chipset recited in claim 7, where the symbol estimator comprises a Rake receiver.

11. The chipset recited in claim 7, where the symbol estimator comprises an equalizer.

12. A method for interference cancellation comprising:

receiving a signal to produce a signal stream;

generating symbol estimates from said signal stream; and

producing at least one segment of an interference cancelled signal;

wherein at least two consecutive segments of said symbol estimates are used to produce said one segment of an interference cancelled signal.

13. The method recited in claim 12, where said one segment comprises an integer multiple of a symbol length.

14. The method recited in claim 12, where generating symbol estimates comprises performing a Fast Hadamard Transform.

15. The method recited in claim 12, where generating symbol estimates comprises a Rake receiver.

16. The method recited in claim 12, where generating symbol estimates comprises an equalizer.

17. The method recited in claim 12, implemented in a chipset.

18. The method recited in claim 12, implemented in a handset.