System and method of page buffer operation for memory devices

• US 8,086,785 B2
• Filed: 07/06/2007
• Issued: 12/27/2011
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Pyeon, Hong Beom, Kim, Jin-Ki, Oh, HakJune
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US11/822,496
• Publication Number:
  US 20080209108A1
• Time in Patent Office: 1,635 Days
• Field of Search: 711/103, 711/118, 711/154, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Claims

1. A method for controlling a plurality of flash memory devices connected with a controller through a common bus, each of the plurality of flash memory devices having a page buffer and memory cells, the controller having a data storage, the method comprising:

finding at least one accessible flash memory device of the plurality of flash memory devices, wherein finding at least one accessible flash memory device of the plurality of flash memory devices comprises finding at least one flash memory device having a page buffer not storing data;

writing data from the data storage of the controller to the page buffer of the at least one accessible flash memory devices; and

reading back the data at a later time from the page buffer of the at least one accessible flash memory device to the data storage of the controller, before programming the data from the page buffer into the memory cells of the at least one accessible flash memory device.

2. The method of claim 1 further comprising:

freeing up space in the data storage where the data is occupied, upon writing the data from the data storage of the controller to the page buffer of the at least one accessible flash memory device.

3. The method of claim 2 wherein the step of writing comprises:

providing a data load command and data to the at least one accessible flash memory device, the data being transmitted from the data storage of the controller; and

providing a command strobe to the at least one accessible flash memory device,

the page buffer of the at least one accessible flash memory device storing the data in the page buffer thereof in response to the data load command and the command strobe.

4. The method of claim 2 wherein the step of reading back comprises:

enabling the at least one of the accessible flash memory device;

providing a data strobe to the at least one accessible flash memory device,

the data stored in the page buffer of the at least one accessible flash memory device being outputted to the data storage of the controller in response to the data strobe.

5. The method of claim 1 wherein the step of writing comprises:

enabling first and second devices of the at least one accessible flash memory device;

providing a data load command and data to the first and second devices, the data being transmitted from the data storage of the controller; and

providing a command strobe to the first and second devices;

the page buffers of the first and second devices storing the data in the page buffer thereof in response to the data load command and the command strobe.

6. The method of claim 5 wherein the step of providing a data load and data comprises:

providing first data load and data and second data load and data.

7. The method of claim 6 wherein the step of providing first data load and data and second data load and data comprises:

providing the first and second data load simultaneously,

the page buffers of the first and second devices storing the data.

8. The method of claim 7 wherein the step of reading back comprises:

enabling the first and second devices;

providing a data strobe to the first and second devices, and

the data stored in the page buffers of the enabled first and second devices being outputted to the data storage of the controller in response to the data strobe.

9. The method of claim 6 wherein the step of providing first data load and data and second data load and data comprises:

providing the first data load and first data and the second data load and second data in different timing,

the page buffers of the first and second devices storing the first and second data, respectively.

10. The method of claim 9 wherein the step of reading back comprises:

enabling the first and second devices;

providing a data strobe; and

the data stored in the page buffers of the enabled first and second devices being outputted to the data storage of the controller in response to the data strobe.

11. An apparatus for controlling a plurality of flash memory devices connected with a common bus, each of the devices having a page buffer and memory cells, the apparatus having a data storage, the apparatus being configured to:

find at least one accessible flash memory device of the plurality of flash memory devices by finding at least one flash memory device having a page buffer not storing data;

write data from the data storage to the page buffer of the at least one accessible flash memory device of the plurality of flash memory devices; and

read back the data at a later time from the page buffer of the at least one accessible flash memory device to the data storage, before programming the data from the page buffer into the memory cells of the at least one accessible device.

12. The apparatus of claim 11 being further configured to:

free up space in the data storage where the data is occupied, upon writing the data from the data storage to the page buffer of the designated device.

13. A system comprising:

a plurality of devices connected with a common bus, each of the devices having a page buffer and memory cells; and

a memory controller for controlling the plurality of devices, the memory controller being configured to;

find at least one accessible flash memory device of the plurality of flash memory devices by finding at least one flash memory device having a page buffer not storing data;

write data from a data storage of the controller to the page buffer of a at least one accessible device; and

read back the data at a later time from the page buffer of the at least one accessible device to the data storage of the controller, before programming the data from the page buffer into the memory cells of the at least one accessible device.

14. The system of claim 13 wherein the memory controller is further configured to:

free up space in the data storage where the data is occupied, upon writing the data from the data storage of the controller to the page buffer of the at least one accessible device.

15. The system of claim 13 wherein each device of the plurality of devices comprises a flash memory device.

16. The system of claim 15 wherein each flash memory device comprises a NAND flash device.