Non-volatile memory device having assignable network identification

• US 8,086,790 B2
• Filed: 03/03/2011
• Issued: 12/27/2011
• Est. Priority Date: 10/09/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/039,802
• Publication Number:
  US 20110153922A1
• Time in Patent Office: 299 Days
• Field of Search: 711/102, 711/103, 711/154, 709/208, 709/226
• US Class Current: 711/103
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.

Claims

1. A memory device comprising:

a plurality of memory dies, each die having a different network identifier that uniquely identifies its respective memory die;

an internal data bus coupled to the plurality of memory dies;

a memory controller configured to control access to the internal data bus by each memory die responsive to the respective network identifier of each memory die.

2. The memory device of claim 1 wherein each network identifier is hard coded into its respective memory die.

3. The memory device of claim 1 and further including a plurality of input/output pins coupled to the internal data bus wherein the memory controller is configured to control access to the plurality of input/output pins by each memory die responsive to the respective network identifier of each memory die.

4. The memory device of claim 1 wherein each network identifier is loadable into its respective memory die.

5. The memory device of claim 1 wherein each memory die comprises an array of non-volatile memory cells.

6. The memory device of claim 1 wherein the array of non-volatile memory cells are floating gate memory cells.

7. The memory device of claim 1 wherein each memory die is configured to broadcast its respective network identifier to the memory controller.

8. The memory device of claim 7 wherein each memory die is further configured to broadcast an amount of data to be transmitted or received on the internal data bus.

9. The memory device of claim 7 wherein each memory die is further configured to broadcast an amount of time to be coupled to the internal data bus.

10. The memory device of claim 7 wherein the memory controller is further configured to schedule access to the internal data bus amongst the plurality of memory dies.

11. The memory device of claim 1 wherein each network identifier is loaded into its respective memory die by an end user.

12. A memory device comprising:

a plurality of memory dies, each die comprising;

a unique network identifier that identifies its respective memory die; and

a bus controller;

an internal data bus coupled to each memory die;

wherein each bus controller is configured to control access to the internal data bus by each memory die responsive to the respective network identifier of each memory die.

13. The memory device of claim 12 wherein each memory die is configured to broadcast its unique network identification and intentions of the memory die on the internal data bus.

14. The memory device of claim 13 wherein each bus controller is configured to receive broadcast network identifications and relinquish control of the internal data bus at a designated time.

15. The memory device of claim 13 wherein a format of the broadcast is responsive to a bus protocol of the respective bus controller.

16. A method for communicating over an internal data bus of a memory device, the method comprising:

a memory die of a plurality of memory dies, each memory die comprising a unique network identification, broadcasting its respective network identification to a bus controller; and

the bus controller enabling access to the internal data bus responsive to the network identification.

17. The method of claim 16 and further comprising the bus controller generating an access schedule for access to the internal data bus by the plurality of memory dies.

18. The method of claim 17 and further comprising transmitting the access schedule to the plurality of memory dies.

19. The method of claim 17 and further comprising transmitting a proceed command to a requesting memory die of the plurality of memory dies responsive to the respective network identification of the requesting memory die and the access schedule.

20. The method of claim 16 and further comprising the memory die transmitting an amount of data or length of time to access the internal data bus with the respective network identification.