Semiconductor integrated circuit apparatus

• US 8,086,814 B2
• Filed: 04/12/2010
• Issued: 12/27/2011
• Est. Priority Date: 03/13/2006
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Shimura, Hidekichi
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Ahmed, Hamdy S
• Application Number:
  US12/758,207
• Publication Number:
  US 20100194455A1
• Time in Patent Office: 624 Days
• Field of Search: 711/167
• US Class Current: 711/167
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers

Abstract

A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock generation circuit. The phase locked loop circuit generates a clock signal in the plurality of function blocks, using the main clock signal from the main clock generation circuit.

Claims

1. A semiconductor integrated circuit apparatus comprising:

a first function block that comprises an internal memory storing an operation program and a processor that performs the operation program;

a second function block that comprises a first clock generation circuit including a first phase locked loop circuit; and

a third function block that comprises a second clock generation circuit including a second phase locked loop circuit, wherein;

the internal memory stores, in a form of a program, work contents of the second and third function blocks, an operating frequency for executing each of the work contents in a predetermined time, a power supply voltage that operates the second and third function blocks at the operating frequency, and a frequency division ratio of a phase locked loop to set in the first and second clock generation circuits so that the second and third function blocks operate at the operating frequency;

when the work content of the second function block is determined, the processor directs a power regulator to supply a necessary power supply voltage to the second function block with reference to the operation program stored in the internal memory, and sets the frequency division ratio of the phase locked loop in the first clock generation circuit of the second function block so that the second function block operates at the operating frequency of the work content;

when the work content of the third function block is determined, the processor directs the power regulator to supply a necessary power supply voltage to the third function block with reference to the program stored in the internal memory, and sets the frequency division ratio of the second phase locked loop in the second clock generation circuit of the third function block so that the third function block operates at the operating frequency of the work content; and

the first and second clock generation circuits generate a clock of a necessary operation frequency, using a clock signal from a main clock generation circuit, based on a frequency division ratio of the phase locked loop set by the processor.

2. The semiconductor integrated circuit apparatus according to claim 1, wherein the processor reads power supply voltages necessary for operating the determined work contents of the second function block and the third function block stored in the internal memory, reads frequency division ratios of the first phase locked loop circuit and the second phase locked loop circuit stored in the internal memory, and provides the read power supply voltages and the read frequency division ratios to the first phase locked loop circuit and the second phase locked loop circuit.

3. The semiconductor integrated circuit apparatus according to claim 1, wherein the first function block comprises a central processing unit, as the processor, and each of the second function block and the third function block comprises a digital signal processor.

4. The semiconductor integrated circuit apparatus according to claim 3, wherein the internal memory is one of a register file or a cache memory.

5. The semiconductor integrated circuit apparatus according to claim 4, wherein the second function block and the third function block respectively comprise internal memories,

the semiconductor integrated circuit further comprising a direct memory access controller that controls mutual reading/writing between the internal memories in the second function block and the third function block.

6. The semiconductor integrated circuit apparatus according to claim 1, wherein each of the first function block, second function block and the third function block includes a selector that selects a clock signal from the clock signals generated by the second clock generation circuit and the third clock generation circuit.