Performing error correction at a memory device level that is transparent to a memory channel
First Claim
1. A memory system comprising:
- a memory hub device integrated in a memory module; and
a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;
first error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices;
second error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, wherein the second error correction logic checks the write data from the link interface for errors;
first error correction code generation logic in the write logic integrated in the memory hub device, wherein the first error correction code generation logic generates a first error correction codeword that is added to the write data before transmitting the write data to the set of memory devices; and
a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.
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Accused Products
Abstract
A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.
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Citations
20 Claims
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1. A memory system comprising:
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a memory hub device integrated in a memory module; and a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises; first error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; second error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, wherein the second error correction logic checks the write data from the link interface for errors; first error correction code generation logic in the write logic integrated in the memory hub device, wherein the first error correction code generation logic generates a first error correction codeword that is added to the write data before transmitting the write data to the set of memory devices; and a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing system, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising; a memory hub device integrated in the memory module; and a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises; first error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; second error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, wherein the second error correction logic checks the write data from the link interface for errors; first error correction code generation logic in the write logic integrated in the memory hub device, wherein the first error correction code generation logic generates a first error correction codeword that is added to the write data before transmitting the write data to the set of memory devices; and a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel. - View Dependent Claims (12, 13, 14, 15)
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16. A method for performing error correction operations in a memory module, comprising:
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receiving, in a memory hub device integrated in the memory module, an access request for accessing a set of memory devices of the memory module coupled to the memory hub device; transferring data between a link interface of the memory hub device and the set of memory devices; and performing, by first error correction logic and second error correction logic integrated in the memory hub device, one or more error correction operations on the data transferred between the link interface and the set of memory devices, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel, wherein the first error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; wherein the second error correction logic is provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, wherein the second error correction logic checks the write data from the link interface for errors; and wherein the memory hub device further comprises first error correction code generation logic in the write logic integrated in the memory hub device, and wherein the first error correction code generation logic generates a first error correction codeword that is added to the write data before transmitting the write data to the set of memory devices. - View Dependent Claims (17, 18, 19, 20)
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Specification